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| * MIPS: Alchemy: preset loops_per_jiffy based on CPU clockManuel Lauss2015-02-202-0/+9
| * MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculationManuel Lauss2015-02-201-5/+14
| * MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill2015-02-203-4/+5
| * MIPS: Usage and cosmetic cleanups of page table bits.Steven J. Hill2015-02-192-62/+38
| * Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/...Ralf Baechle2015-02-1965-415/+4405
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| | * MIPS: Add Malta QEMU 32R6 defconfigMarkos Chandras2015-02-171-0/+193
| | * MIPS: Malta: Add support for building MIPS R6 kernelMarkos Chandras2015-02-171-0/+2
| | * MIPS: kernel: elf: Improve the overall ABI and FPU mode checksMarkos Chandras2015-02-173-132/+194
| | * MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6Markos Chandras2015-02-171-1/+2
| | * MIPS: kernel: process: Do not allow FR=0 on MIPS R6Markos Chandras2015-02-171-0/+4
| | * MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2015-02-172-5/+6
| | * MIPS: Make use of the ERETNC instruction on MIPS R6Markos Chandras2015-02-175-4/+28
| | * MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6Leonid Yegoshin2015-02-178-5/+2518
| | * MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras2015-02-171-0/+2
| | * MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-174-0/+7
| | * MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras2015-02-173-1/+20
| | * MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras2015-02-173-1/+16
| | * MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras2015-02-173-1/+19
| | * MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras2015-02-173-2/+7
| | * MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras2015-02-173-1/+21
| | * MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras2015-02-173-1/+23
| | * MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructionsMarkos Chandras2015-02-172-0/+47
| | * MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructionsMarkos Chandras2015-02-172-0/+55
| | * MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras2015-02-173-30/+101
| | * MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6Markos Chandras2015-02-172-13/+89
| | * MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6Markos Chandras2015-02-173-2/+15
| | * MIPS: mm: scache: Add secondary cache support for MIPS R6 coresMarkos Chandras2015-02-172-2/+4
| | * MIPS: mm: c-r4k: Set the correct ISA levelMarkos Chandras2015-02-171-1/+1
| | * MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instructionLeonid Yegoshin2015-02-171-3/+3
| | * MIPS: mm: page: Add MIPS R6 supportMarkos Chandras2015-02-171-4/+26
| | * MIPS: lib: memset: Add MIPS R6 supportLeonid Yegoshin2015-02-171-0/+47
| | * MIPS: lib: memcpy: Add MIPS R6 supportLeonid Yegoshin2015-02-171-0/+23
| | * MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-1/+1
| | * MIPS: kernel: unaligned: Add support for the MIPS R6Leonid Yegoshin2015-02-171-4/+386
| | * MIPS: kernel: cps-vec: Replace "addi" with "addiu"Markos Chandras2015-02-171-8/+8
| | * MIPS: kernel: genex: Set correct ISA levelMarkos Chandras2015-02-171-1/+1
| | * MIPS: kernel: r4k_fpu: Add support for MIPS R6Leonid Yegoshin2015-02-171-3/+9
| | * MIPS: kernel: r4k_switch: Add support for MIPS R6Leonid Yegoshin2015-02-172-11/+15
| | * MIPS: kernel: traps: Add MIPS R6 related definitionsLeonid Yegoshin2015-02-171-5/+5
| | * MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras2015-02-172-1/+10
| | * MIPS: kernel: entry.S: Add MIPS R6 related definitionsMarkos Chandras2015-02-171-2/+3
| | * MIPS: kernel: cpu-probe.c: Add support for MIPS R6Leonid Yegoshin2015-02-171-4/+16
| | * MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handlerLeonid Yegoshin2015-02-171-1/+1
| | * MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugsLeonid Yegoshin2015-02-171-4/+7
| | * MIPS: asm: local: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-2/+3
| | * MIPS: asm: spinlock: Replace "sub" instruction with "addiu"Markos Chandras2015-02-171-5/+2
| | * MIPS: asm: futex: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-4/+4
| | * MIPS: asm: bitops: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-15/+15
| | * MIPS: asm: atomic: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-6/+6
| | * MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-5/+5
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