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* MIPS: KVM: Wire up MSA capabilityJames Hogan2015-03-271-0/+18
* MIPS: KVM: Expose MSA registersJames Hogan2015-03-272-2/+75
* MIPS: KVM: Add MSA exception handlingJames Hogan2015-03-275-2/+140
* MIPS: KVM: Emulate MSA bits in COP0 interfaceJames Hogan2015-03-271-2/+35
* MIPS: KVM: Add base guest MSA supportJames Hogan2015-03-276-19/+323
* MIPS: KVM: Wire up FPU capabilityJames Hogan2015-03-271-0/+37
* MIPS: KVM: Expose FPU registersJames Hogan2015-03-272-11/+98
* MIPS: KVM: Add FP exception handlingJames Hogan2015-03-275-3/+88
* MIPS: KVM: Emulate FPU bits in COP0 interfaceJames Hogan2015-03-271-11/+100
* MIPS: KVM: Add base guest FPU supportJames Hogan2015-03-277-1/+333
* MIPS: KVM: Add vcpu_get_regs/vcpu_set_regs callbackJames Hogan2015-03-273-0/+20
* MIPS: KVM: Add Config4/5 and writing of Config registersJames Hogan2015-03-274-2/+126
* MIPS: KVM: Simplify default guest Config registersJames Hogan2015-03-272-31/+9
* MIPS: KVM: Clean up register definitions a littleJames Hogan2015-03-272-55/+68
* MIPS: KVM: Drop pr_info messages on init/exitJames Hogan2015-03-271-3/+0
* MIPS: KVM: Sort kvm_mips_get_reg() registersJames Hogan2015-03-271-3/+3
* MIPS: KVM: Implement PRid CP0 register accessJames Hogan2015-03-272-0/+8
* MIPS: KVM: Handle TRAP exceptions from guest kernelJames Hogan2015-03-275-0/+71
* MIPS: Clear [MSA]FPE CSR.Cause after notify_die()James Hogan2015-03-273-12/+21
* MIPS: KVM: Handle MSA Disabled exceptions from guestJames Hogan2015-03-274-0/+35
* MIPS: MSA: Fix big-endian FPR_IDX implementationJames Hogan2015-03-271-1/+1
* Revert "MIPS: Don't assume 64-bit FP registers for context switch"James Hogan2015-03-273-194/+128
* MIPS: disable FPU if the mode is unsupportedPaul Burton2015-03-271-7/+12
* MIPS: prevent FP context set via ptrace being discardedPaul Burton2015-03-271-6/+24
* MIPS: Ensure FCSR cause bits are clear after invoking FPU emulatorPaul Burton2015-03-271-8/+9
* MIPS: clear MSACSR cause bits when handling MSA FP exceptionPaul Burton2015-03-271-1/+10
* MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA supportPaul Burton2015-03-271-4/+20
* MIPS: remove MSA macro recursionPaul Burton2015-03-271-3/+31
* MIPS: assume at as source/dest of MSA copy/insert instructionsPaul Burton2015-03-271-16/+12
* MIPS: Push .set mips64r* into the functions needing itPaul Burton2015-03-272-9/+5
* MIPS: lose_fpu(): Disable FPU when MSA enabledJames Hogan2015-03-271-0/+1
* KVM: MIPS: Enable after disabling interruptTapasweni Pathak2015-03-021-0/+1
* KVM: MIPS: Fix trace event to save PC directlyJames Hogan2015-03-021-3/+3
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-02-21105-1123/+6390
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| * MIPS: sead3: Corrected get_c0_perfcount_intNiklas Cassel2015-02-201-1/+1
| * MIPS: mm: Remove dead macro definitionsAndreas Ruprecht2015-02-202-16/+0
| * MIPS: OCTEON: irq: add CIB and other fixesDavid Daney2015-02-201-269/+780
| * MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.David Daney2015-02-201-2/+43
| * MIPS: OCTEON: More OCTEONIII supportChandrakala Chavva2015-02-204-2/+326
| * MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.Chad Reese2015-02-201-20/+0
| * MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.David Daney2015-02-202-6/+17
| * MIPS: OCTEON: Update octeon-model.h code for new SoCs.David Daney2015-02-205-27/+90
| * MIPS: OCTEON: Implement DCache errata workaround for all CN6XXXDavid Daney2015-02-203-4/+8
| * MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.hDavid Daney2015-02-201-30/+105
| * MIPS: OCTEON: Implement the core-16057 workaroundDavid Daney2015-02-201-0/+22
| * MIPS: OCTEON: Delete unused COP2 saving codeAleksey Makarov2015-02-201-26/+0
| * MIPS: OCTEON: Use correct instruction to read 64-bit COP0 registerChandrakala Chavva2015-02-201-3/+3
| * MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney2015-02-203-11/+35
| * MIPS: OCTEON: Fix FP context save.David Daney2015-02-201-12/+7
| * MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney2015-02-204-32/+150
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