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git://git.infradead.org/users/dhowells/linux-headers
UAPI Disintegration 2012-10-09
Conflicts:
MAINTAINERS
arch/arm/configs/bcmring_defconfig
arch/arm/mach-imx/clk-imx51-imx53.c
drivers/mtd/nand/Kconfig
drivers/mtd/nand/bcm_umi_nand.c
drivers/mtd/nand/nand_bcm_umi.h
drivers/mtd/nand/orion_nand.c
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Merge patches from Andrew Morton:
"A few misc things and very nearly all of the MM tree. A tremendous
amount of stuff (again), including a significant rbtree library
rework."
* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (160 commits)
sparc64: Support transparent huge pages.
mm: thp: Use more portable PMD clearing sequenece in zap_huge_pmd().
mm: Add and use update_mmu_cache_pmd() in transparent huge page code.
sparc64: Document PGD and PMD layout.
sparc64: Eliminate PTE table memory wastage.
sparc64: Halve the size of PTE tables
sparc64: Only support 4MB huge pages and 8KB base pages.
memory-hotplug: suppress "Trying to free nonexistent resource <XXXXXXXXXXXXXXXX-YYYYYYYYYYYYYYYY>" warning
mm: memcg: clean up mm_match_cgroup() signature
mm: document PageHuge somewhat
mm: use %pK for /proc/vmallocinfo
mm, thp: fix mlock statistics
mm, thp: fix mapped pages avoiding unevictable list on mlock
memory-hotplug: update memory block's state and notify userspace
memory-hotplug: preparation to notify memory block's state at memory hot remove
mm: avoid section mismatch warning for memblock_type_name
make GFP_NOTRACK definition unconditional
cma: decrease cc.nr_migratepages after reclaiming pagelist
CMA: migrate mlocked pages
kpageflags: fix wrong KPF_THP on non-huge compound pages
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.fault now can retry. The retry can break state machine of .fault. In
filemap_fault, if page is miss, ra->mmap_miss is increased. In the second
try, since the page is in page cache now, ra->mmap_miss is decreased. And
these are done in one fault, so we can't detect random mmap file access.
Add a new flag to indicate .fault is tried once. In the second try, skip
ra->mmap_miss decreasing. The filemap_fault state machine is ok with it.
I only tested x86, didn't test other archs, but looks the change for other
archs is obvious, but who knows :)
Signed-off-by: Shaohua Li <shaohua.li@fusionio.com>
Cc: Rik van Riel <riel@redhat.com>
Cc: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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The core page allocator ensures that page flags are zeroed when freeing
pages via free_pages_check. A number of architectures (ARM, PPC, MIPS)
rely on this property to treat new pages as dirty with respect to the data
cache and perform the appropriate flushing before mapping the pages into
userspace.
This can lead to cache synchronisation problems when using hugepages,
since the allocator keeps its own pool of pages above the usual page
allocator and does not reset the page flags when freeing a page into the
pool.
This patch adds a new architecture hook, arch_clear_hugepage_flags, so
that architectures which rely on the page flags being in a particular
state for fresh allocations can adjust the flags accordingly when a page
is freed into the pool.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: Michal Hocko <mhocko@suse.cz>
Reviewed-by: Michal Hocko <mhocko@suse.cz>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Introduce HAVE_DEBUG_KMEMLEAK config option and select it in corresponding
architecture Kconfig files. DEBUG_KMEMLEAK now only depends on
HAVE_DEBUG_KMEMLEAK.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
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mips-for-linux-next
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These were erroneously copied from BCM6368. BCM6328 does not expose the
ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used
for the second UART.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4090/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Makes the code a bit more readable and easier to add support for
new chips.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4093/
Signed-off-by: John Crispin <blogic@openwrt.org>
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While harmless, it is bad style to do so.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4092/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Add the missing definitions for BCM6345.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4091/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Needed by SPI driver.
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/3796/
Signed-off-by: John Crispin <blogic@openwrt.org>
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VSMP kernel build for non-malta platforms fails with following error
LD init/built-in.o
LD .tmp_vmlinux1
arch/mips/built-in.o: In function `vsmp_init_secondary':
smp-mt.c:(.cpuinit.text+0x23cc): undefined reference to `gic_present'
smp-mt.c:(.cpuinit.text+0x23d0): undefined reference to `gic_present'
make: *** [.tmp_vmlinux1] Error 1
gic_present variable is declared only if IRQ_GIC is selected.
Signed-off-by: Anoop P A <anoop.pa@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/2039/
Signed-off-by: John Crispin <blogic@openwrt.org>
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R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
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R4K-style CPUs have this boolean defined by default. Allows us
to remove some lines in arch/mips/kernel/Makefile.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3330/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Allows us not to duplicate more lines in arch/mips/lib/Makefile.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3329/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Enable more devices and options for XLP default configuration:
- Serial ports from FDT
- NOR Flash support and partitions from FDT
- PCI and PCI bus support and devices - SATA, e1000e, sky2
- I2C ocores controller and devices - ds1374, lm90
- Misc options such as RTC, partition formats etc.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
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Provide a config option to embed a device tree for XLP evaluation
boards. This DTB will be used if the firmware does not pass in a
device tree pointer.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4103/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Add the serial ports to the device tree and remove the platform
code for adding them.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4098/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Add a basic DTS file netlogic/dts/nlm_xlp.dts which contains
memory, i2c devices, NOR flash and command line arguments.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4100/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Move the function device_tree_init() from netlogic/xlp/of.c
to setup.c, and remove the wrapper functions reserve_mem_mach()
and free_mem_mach().
Remove file netlogic/xlp/of.c, and the Makefile entry for it.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4097/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Previously we relied on the bootloader to have enabled this bit. However some
bootloaders seem to not enable this for us.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4120/
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Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.
Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The current dividers in the code are wrong and this
leads to broken CPU frequency calculation on boards
where the fractional part is used.
For example, if the SoC is running from a 40MHz
reference clock, refdiv=1, nint=14, outdiv=0 and
nfrac=31 the real frequency is 579.375MHz but the
current code calculates 569.687MHz instead.
Because the system time is indirectly related to
the CPU frequency the broken computation causes
drift in the system time.
The correct divider is 2^6 for the CPU PLL and 2^10
for the DDR PLL. Use the correct values to fix the
issue.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: stable@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4305/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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While calculating the mac address the pointer for the current octet was
never reset back to the least significant one after being decremented
because of an octet overflow. This resulted in the code continuing to
increment at the current octet, potentially generating duplicate or
invalid mac addresses.
As a second issue the pointer was allowed to advance up to the most
significant octet, modifying the OUI, and potentially changing the type
of mac address.
Rewrite the code so it resets the pointer to the least significant
in each outer loop step, and bails out when the least significant octet
of the OUI is reached.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
Patchwork: https://patchwork.linux-mips.org/patch/4348/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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b01da9f1 ("MIPS: Prune some target specific code out of prom.c") removed
the generic implementation of device_tree_init, breaking the kernel
build when manually selecting USE_OF.
Hide the config symbol so it can't be selected acidentially anymore.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/4346/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
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The EXT and INS instructions can be used to decrease code size and
thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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When dealing with multiple VPEs, the count needs to be one-based
for correct initialization of the GIC.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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Each platform should define its own 'gic_finish_irq' function.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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Add support to use an external interrupt controller with the GIC.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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Fix whitespace, beautify the code and remove debug statements.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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Change MIPS configuration files to add the SEAD-3. Also add
new default configuration file for a SEAD-3 kernel.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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More information about the SEAD-3 platform can be found at
<http://www.mips.com/products/development-kits/mips-sead-3/>
on MTI's site. Currently, the M14K family of cores is what
the SEAD-3 is utilised with.
Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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Signed-off-by: Steven J. Hill <sjhill@mips.com>
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git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
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Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
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Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
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mips-for-linux-next
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Reviewed-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4111/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4084/
Signed-off-by: John Crispin <blogic@openwrt.org>
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OHCI/EHCI are in the high (second) word. Not currently used by any
driver.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4026/
Signed-off-by: John Crispin <blogic@openwrt.org>
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The USB 2.0 device depends on some functionality in other blocks, such
as GPIO and USBH. Add those register definitions here.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4025/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/
Signed-off-by: John Crispin <blogic@openwrt.org>
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The "IUDMA" engine used by bcm63xx_enet is also used by other blocks,
such as the USB 2.0 device. Move the definitions into a common file so
that they do not need to be duplicated in each driver.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4082/
Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4022/
Signed-off-by: John Crispin <blogic@openwrt.org>
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