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| * | | MIPS: Refactor dumping of TLB registers for r3k/r4kJames Hogan2015-09-036-28/+34
| * | | MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructionsMarkos Chandras2015-09-031-1/+19
| * | | MIPS: math-emu: Allow m{f,t}hc emulation on MIPS R6Markos Chandras2015-09-031-2/+2
| * | | MIPS: math-emu: Fix indentationMarkos Chandras2015-09-031-4/+4
| * | | MIPS: cp1emu: Fix closing bracket for the d_fmt caseMarkos Chandras2015-09-031-1/+4
| * | | MIPS: Kconfig: Drop the EXPERIMENTAL tag from MIPS R6Markos Chandras2015-09-031-2/+2
| * | | MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle2015-09-031-1/+1
| * | | MIPS: Use unsigned int when reading CP0 registersChris Packham2015-09-031-2/+2
| * | | MIPS: malta: Use generic platform_maar_initPaul Burton2015-09-031-25/+0
| * | | MIPS: mm: default platform_maar_init using bootmem dataPaul Burton2015-09-031-2/+34
| * | | MIPS: MSA unaligned memory access supportLeonid Yegoshin2015-09-031-0/+72
| * | | MIPS: Introduce accessors for MSA vector registersPaul Burton2015-09-033-0/+261
| * | | MIPS: Declare MSA MI10 instruction formatsLeonid Yegoshin2015-09-031-1/+30
| * | | MIPS: Remove "__weak" definition from arch-specific linkage.hBjorn Helgaas2015-09-031-1/+0
| * | | MIPS: Remove "weak" from mips_cdmm_phys_base() declarationBjorn Helgaas2015-09-031-2/+2
| * | | MIPS: Remove "weak" from get_c0_fdc_int() declarationBjorn Helgaas2015-09-031-1/+1
| * | | MIPS: Remove "weak" from get_c0_compare_int() declarationBjorn Helgaas2015-09-032-5/+8
| * | | MIPS: MT: Remove "weak" from vpe_run() declarationBjorn Helgaas2015-08-262-6/+6
| * | | MIPS: VPE: Exit vpe_release() early if vpe_run() isn't definedBjorn Helgaas2015-08-261-1/+6
| * | | MIPS: Remove "weak" from platform_maar_init() declarationBjorn Helgaas2015-08-261-1/+1
| * | | MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it staticBjorn Helgaas2015-08-262-11/+8
| * | | MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.hPaul Burton2015-08-262-57/+0
| * | | MIPS: ops-emma2rh: Drop nonsensical db_assertPaul Burton2015-08-261-4/+2
| * | | MIPS: rt3883: Prepare rt3883_pci_irq_handler for irq argument removalThomas Gleixner2015-08-261-2/+2
| * | | MIPS: netlogic: Prepare ipi handlers for irq argument removalThomas Gleixner2015-08-261-2/+4
| * | | MIPS: octeon: Replace the homebrewn flow handlerThomas Gleixner2015-08-261-11/+11
| * | | MIPS: ath91: Remove pointless irqdisable/enableThomas Gleixner2015-08-261-16/+2
| * | | MIPS: alchemy: Remove pointless irqdisable/enableThomas Gleixner2015-08-261-2/+4
| * | | MIPS: bcm63xx: Use irq_set_handler_locked()Thomas Gleixner2015-08-261-2/+2
| * | | MIPS: alchemy: Use irq_set_chip_handler_name_locked()Thomas Gleixner2015-08-261-2/+2
| * | | MIPS: irq: Use access helper irq_data_get_affinity_mask()Jiang Liu2015-08-263-8/+11
| * | | MIPS: pci-rt3883: Consolidate chained IRQ handler install/removeThomas Gleixner2015-08-261-2/+1
| * | | MIPS: pci-ar724x: Consolidate chained IRQ handler install/removeThomas Gleixner2015-08-261-2/+2
| * | | MIPS: pci-ar71xx: Consolidate chained IRQ handler install/removeThomas Gleixner2015-08-261-2/+2
| * | | MIPS: jz4740: Consolidate chained IRQ handler install/removeThomas Gleixner2015-08-261-2/+2
| * | | MIPS: Set up FTLB probability for I6400Markos Chandras2015-08-262-5/+15
| * | | MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6Markos Chandras2015-08-261-1/+10
| * | | MIPS: Add default case for the FTLB enable/disable codeMarkos Chandras2015-08-261-3/+10
| * | | MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLBMarkos Chandras2015-08-261-1/+0
| * | | MIPS: CM: Add support for reporting CM cache errorsMarkos Chandras2015-08-263-111/+254
| * | | MIPS: CPC: Fix type for GCR CPC base reg for 64-bitMarkos Chandras2015-08-261-1/+1
| * | | MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.Markos Chandras2015-08-261-1/+1
| * | | MIPS: mips-cm: Extend CM accessors for 64-bit CPUsMarkos Chandras2015-08-262-4/+48
| * | | MIPS: Add platform callback before initializing the L2 cacheMarkos Chandras2015-08-263-0/+24
| * | | MIPS: CM3: Add support for CM3 L2 cache.Paul Burton2015-08-261-0/+32
| * | | MIPS: CM: Add GCR_L2_CONFIG register accessorsPaul Burton2015-08-261-0/+11
| * | | MIPS: mips-cm: Implement mips_cm_revisionPaul Burton2015-08-261-0/+21
| * | | MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6Markos Chandras2015-08-261-3/+3
| * | | MIPS: Add MIPS I6400 probe supportMarkos Chandras2015-08-261-0/+4
| * | | MIPS: Add cases for CPU_I6400Markos Chandras2015-08-269-0/+21
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