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* MIPS: generic: Convert SEAD-3 to a generic boardPaul Burton2016-10-061-91/+0
| | | | | | | | | | | | | | | | | | | | | Convert the MIPS SEAD-3 board support to be a generic board, supported by generic kernels. Because the SEAD-3 boot protocol was defined long ago and we don't want to force a switch to the UHI protocol, SEAD-3 is added as a legacy board which is detected by reading the REVISION register. This may technically not be a valid memory read & future work will include attempting to handle that gracefully. In practice since SEAD-3 is the only legacy board supported by the generic kernel so far the read will only happen on SEAD-3 boards, and even once Malta is converted the same REVISION register exists there too. Other boards such as Boston, Ci20 & Ci40 will use the UHI boot protocol & thus not run any of the legacy board detect functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SEAD3: Remove custom read_persistent_clockPaul Burton2016-10-061-6/+0
| | | | | | | | | | | | The SEAD3 board defines a custom implementation of read_persistent_clock which does exactly the same dummy operation as the generic weak version. Remove the not really implemented custom version. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14064/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SEAD3: Use img-ascii-lcd driverPaul Burton2016-10-061-2/+0
| | | | | | | | | | | | | | | | | Probe the img-ascii-lcd driver using device tree in order to display a message on the SEAD3 board's LCD display, and remove the platform code that was formerly performing this function. This removes more platform code and moves SEAD3 further towards being entirely DT-based. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Jacek Anaszewski <j.anaszewski@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14063/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Export get_c0_perfcount_int()Felix Fietkau2015-08-031-0/+1
| | | | | | | | | | | | | | get_c0_perfcount_int is tested from oprofile code. If oprofile is compiled as module, get_c0_perfcount_int needs to be exported, otherwise it cannot be resolved. Fixes: a669efc4a3b4 ("MIPS: Add hook to get C0 performance counter interrupt") Cc: stable@vger.kernel.org # v3.19+ Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: linux-mips@linux-mips.org Cc: abrestic@chromium.org Patchwork: https://patchwork.linux-mips.org/patch/10763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: sead3: Corrected get_c0_perfcount_intNiklas Cassel2015-02-201-1/+1
| | | | | | | | | | | Commit e9de688dac65 ("irqchip: mips-gic: Support local interrupts") updated several platforms. This is a copy paste error. Signed-off-by: Niklas Cassel <niklass@axis.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9245/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move gic.h to include/linux/irqchip/mips-gic.hAndrew Bresticker2014-11-241-1/+1
| | | | | | | | | | | | | | | | | Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Support local interruptsAndrew Bresticker2014-11-241-25/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker2014-11-241-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7805/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: sead3: remove unused cpu_khz variablePaul Burton2014-01-231-4/+0
| | | | | | | | | | | This variable seems to have been copied from Malta when SEAD3 support was introduced, but is likewise unused. Remove it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6172/
* MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki2013-09-181-1/+2
| | | | | | | | | | Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: FW: Remove obsolete header file for MTI platforms.Steven J. Hill2013-05-081-1/+0
| | | | | | | | | | | | | | | Remove 'arch/mips/include/asm/mips-boards/prom.h' and get rid of all inclusions of it by Malta and SEAD-3 platforms. [ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS: ar7 powertv build"]. [ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS: unbreak powertv build"]. [ralf@linux-mips.org: Test. Build. Your. Fscking. Code. Or...] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-4/+4
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add core files for MIPS SEAD-3 development platform.Steven J. Hill2012-09-131-0/+117
More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
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