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* MIPS: malta: malta-init: Fix System Controller memory mapping for EVALeonid Yegoshin2014-03-261-0/+13
| | | | | | | Shift System Controller memory mapping to 0x80000000 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Add free_init_pages_eva() callbackMarkos Chandras2014-03-261-0/+8
| | | | | | | | | Use a Malta specific function to free the init section once the kernel has booted. When operating in EVA mode, the physical memory is shifted to 0x80000000. Kernel is loaded into 0x80000000 (virtual) so the offset between physical and virtual addresses is 0. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory mapMarkos Chandras2014-03-261-7/+7
| | | | | | | | | PHYS_OFFSET is used to denote the physical start address of the first bank of RAM. When the Malta board is in EVA mode, the physical start address of RAM is shifted to 0x80000000 so it's necessary to use this macro in order to make the code EVA agnostic. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras2014-03-261-9/+27
| | | | | | | | | | | The 'ememsize' variable is used to denote the real RAM which is present on the Malta board. This is different compared to 'memsize' which is capped to 256MB. The 'ememsize' is used to get the actual physical memory when setting up the Malta memory layout. This only makes sense in case the core operates in the EVA mode, and it's ignored otherwise. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000 - 0x7fffffff ignoring the 256 MB IO hole in 0x10000000. The physical memory is shifted to 0x80000000 so up to 2GB can be used. Kuseg is expanded to 3GB (due to board limitations only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB. The Segment Control registers are programmed as follows: Virtual memory Physical memory Mapping 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 0xc0000000 - 0xdfffffff - MK (kseg2) 0xe0000000 - 0xffffffff - MK (kseg3) The location of exception vectors remain the same since 0xbfc00000 (traditional exception base) still maps to 0x1fc00000 physical. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Malta: Allow use of MIPS CPS SMP implementationPaul Burton2014-03-261-0/+2
| | | | | | | | | | | | | This patch simply attempts to register the MIPS Coherent Processing System SMP implementation when it is enabled. If registering that fails for some reason (like the Kconfig option being disabled or a lack of hardware support) then we fall back to the same SMP implementations as before. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6365/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Probe CPC when supportedPaul Burton2014-03-261-0/+7
| | | | | | | | | | | When CPC support is compiled into the kernel (ie. CONFIG_MIPS_CPC=y), probe the CPC on boot for Malta in order to allow any users of the CPC to detect its presence & function correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6363/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Make use of generic CM supportPaul Burton2014-03-263-63/+19
| | | | | | | | | | Remove the Malta-specific CM probe code and instead make use of the newly added generic CM code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6364/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-01-241-1/+0
| | | | | | | | | | | None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6320/
* MIPS: Malta: use generic 8250 early consolePaul Burton2014-01-233-74/+33
| | | | | | | | | | | | | | | | | | | | | | | This patch switches Malta from using the MIPS implementation of early printk with Malta's prom_putchar to using the generic 8250_early implementation. This offers a couple of advantages: - We duplicate less generic code. - The UART can be initialised rather than being reliant upon inheriting a valid setup from the bootloader. The Malta console_config function is extended to initialise the early console if no earlycon= kernel parameter is provided, inheriting the modetty0 bootloader environment if present and falling back to a default 38400n8r setup if not. This matches the behaviour used for the regular console= parameter. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6183/
* MIPS: Malta: initialise the RTC at bootPaul Burton2014-01-231-0/+13
| | | | | | | | | | | | | | The RTC is used on Malta to estimate the clock frequency of the CPU & optionally the GIC. However the kernel previously did not initialise the RTC, instead relying upon the bootloader having done so. In order to minimise dependencies which the kernel has upon the bootloader this patch causes the kernel to initialise the RTC itself prior to making use of it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6184/
* MIPS: Malta: remove unused cpu_khz variablePaul Burton2014-01-231-3/+0
| | | | | | | | | | | | This variable was introduced by commit 96348c8f (of Ralf's historic Linux/MIPS repository) "Remaining fixes for MIPS's eval boards." but I don't see any use of it either then or now. Remove it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6171/
* MIPS: APRP: Code formatting clean-ups.Steven J. Hill2014-01-222-76/+63
| | | | | | | | | Clean-up code according to the 'checkpatch.pl' script. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/ Reviewed-by: John Crispin <blogic@openwrt.org>
* MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu2014-01-222-3/+33
| | | | | | | | | | Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6096/
* MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin2014-01-221-0/+2
| | | | | | | | | | | | | | | | | | Commit 225ae5fd9a320e22841410049c3bdb6cf14a5841 "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6045/
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-11-081-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - Some minor work bringing the Cobalt MIPS platforms in line with other MIPS platforms - Make vmlinux.32 and vmlinux.64 build messages less verbose - Always register the R4k clocksource when selected, the clock source's rating will decide if this or another clock source is actually going to be used - Drop support for the Cisco (formerly Scientific Atlanta) PowerTV platform. There appears to be nobody left who cares and the USB driver went stale while waiting for years to be merged - Some cleanup of Loongson 2 related #ifdefery - Various minor cleanups - Major rework on all things related to tracing / ptrace on MIPS, including switching the MIPS ELF core dumper to regsets, enabling the entries for SIGSYS in struct siginfo for MIPS, enabling ftrace syscall trace points - Some more work to bring DECstation support code in line with other more modern code - Report the name of the detected CPU, not just its CP0 PrID value - Some more BCM 47xx and atheros ath79xx work - Support for compressed kernels using the XZ compression scheme * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (53 commits) MIPS: remove duplicate define MIPS: Random whitespace clean-ups MIPS: traps: Reformat notify_die invocations to 80 columns. MIPS: Print correct PC in trace dump after NMI exception MIPS: kernel: cpu-probe: Report CPU id during probe MIPS: Remove unused defines in piix4.h MIPS: Get rid of hard-coded values for Malta PIIX4 fixups MIPS: Always register R4K clock when selected MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips. MIPS: cacheops.h: Increase indentation by one tab. MIPS: Remove bogus BUG_ON() MIPS: PowerTV: Remove support code. MIPS: ftrace: Add support for syscall tracepoints. MIPS: ptrace: Switch syscall reporting to tracehook_report_syscall_entry(). MIPS: Move audit_arch() helper function to __syscall_get_arch(). MIPS: Enable HAVE_ARCH_TRACEHOOK. MIPS: Switch ELF core dumper to use regsets. MIPS: Implement task_user_regset_view. MIPS: ptrace: Use tracehook helpers. MIPS: O32 / 32-bit: Always copy 4 stack arguments. ...
| * MIPS: Remove unused defines in piix4.hDeng-Cheng Zhu2013-10-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PIIX4_ICTLR* and PIIX4_OCW* defines are not used by any other files. Remove them. The only file (other than fixup-malta.c which includes piix4.h in patch #1) containing "#include <asm/mips-boards/piix4.h>" is arch/mips/mti-malta/malta-int.c whose first version is actually "1da177e4c3:arch/mips/mips-boards/malta/malta_int.c". In that version, in the function get_int(), things in piix4.h are used. But now malta-int.c no longer needs those stuff. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: malta: Fix GIC interrupt offsetsMarkos Chandras2013-10-301-4/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC interrupt offsets are calculated based on the value of NR_CPUS. However, this is wrong because NR_CPUS may or may not contain the real number of the actual cpus present in the system. We fix that by using the 'nr_cpu_ids' variable which contains the real number of cpus in the system. Previously, an MT core (eg with 8 VPEs) will fail to boot if NR_CPUS was > 8 with the following errors: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at kernel/irq/chip.c:670 __irq_set_handler+0x15c/0x164() Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00087-gced5633 5 Stack : 00000006 00000004 00000000 00000000 00000000 00000000 807a4f36 00000053 807a0000 00000000 80173218 80565aa8 00000000 00000000 00000000 0000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000000 00000000 00000000 00000000 8054fd00 8054fd94 80500514 805657a7 8016eb4 807a0000 80500514 00000000 00000000 80565aa8 8079a5d8 80565766 8054fd0 ... Call Trace: [<801098c0>] show_stack+0x64/0x7c [<8049c6b0>] dump_stack+0x64/0x84 [<8012efc4>] warn_slowpath_common+0x84/0xb4 [<8012f00c>] warn_slowpath_null+0x18/0x24 [<80173218>] __irq_set_handler+0x15c/0x164 [<80587cf4>] arch_init_ipiirq+0x2c/0x3c [<805880c8>] arch_init_irq+0x3c4/0x4bc [<80588e28>] init_IRQ+0x3c/0x50 [<805847e8>] start_kernel+0x230/0x3d8 ---[ end trace 4eaa2a86a8e2da26 ]--- This is now fixed and the Malta board can boot with any NR_CPUS value which also helps supporting more processors in a single kernel binary. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6091/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki2013-09-181-2/+3
| | | | | | | | | | Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-142-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle2013-07-121-25/+8
|\ | | | | | | | | This that should have been fixed but weren't, way to much, intrusive and late.
| * MIPS: malta: Remove software reset defines from generic header.Steven J. Hill2013-06-211-24/+5
| | | | | | | | | | | | | | | | | | | | | | Remove the software reset register and reset value definitions from the 'include/asm/mips-boards/generic.h' header file. Also clean up header and whitespace in platform file. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5456/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: malta: Move defines of reset registers and values.Steven J. Hill2013-06-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | Remove usage of 'include/asm/mips-boards/generic.h' header file. Instead, move the defines for SOFTRES_REG and GORESET local to the platform file. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5455/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Malta: Update GCMP detection.Leonid Yegoshin2013-07-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | Add GCMP detection for IASim Marvell chip emulation support. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/5529/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Malta: Move platform-specific PCI code to arch/mips/pci.Ralf Baechle2013-07-012-255/+0
|/ | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mti-next' of ↵Ralf Baechle2013-05-098-308/+182
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: Add new GIC clockevent driver.Raghu Gandham2013-05-091-0/+3
| | | | | | | | | | | | | | | | Add new clockevent driver that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Raghu Gandham <Raghu.Gandham@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: Refactor GIC clocksource code.Steven J. Hill2013-05-091-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize some of the GIC clocksource driver code. Below is a list of the various changes. * No longer select CSRC_GIC by default for Malta platform. * Limit choice for either the GIC or R4K clocksource, not both. * Change location in Makefile. * Created new 'gic_read_count' function in common 'irq-gic.c' file. * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function. * Surround GIC specific code in Malta platform code with #ifdef's. * Only initialize the GIC clocksource if it was selected. Original code called it unconditionally if a GIC was found. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: Move 'gic_frequency' to common location.Steven J. Hill2013-05-091-1/+0
| | | | | | | | | | | | | | | | | | Move the global variable 'gic_frequency' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: Move 'gic_present' to common location.Steven J. Hill2013-05-091-1/+0
| | | | | | | | | | | | | | | | | | Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: FW: malta: Code formatting clean-ups.Steven J. Hill2013-05-084-88/+64
| | | | | | | | | | | | Clean-up code according to the 'checkpatch.pl' script. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: FW: Remove obsolete header file for MTI platforms.Steven J. Hill2013-05-084-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove 'arch/mips/include/asm/mips-boards/prom.h' and get rid of all inclusions of it by Malta and SEAD-3 platforms. [ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS: ar7 powertv build"]. [ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS: unbreak powertv build"]. [ralf@linux-mips.org: Test. Build. Your. Fscking. Code. Or...] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: FW: malta: Use new common FW library variable processing.Steven J. Hill2013-05-085-199/+28
| | | | | | | | | | | | Remove old YAMON prom code and use common firmware library code. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: Add option to disable software I/O coherency.Steven J. Hill2013-05-011-0/+63
| | | | | | | | | | | | | | | | | | Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
* | KVM/MIPS32: KVM Guest kernel support.Sanjay Lal2013-05-081-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Both Guest kernel and Guest Userspace execute in UM. The memory map is as follows: Guest User address space: 0x00000000 -> 0x40000000 Guest Kernel Unmapped: 0x40000000 -> 0x60000000 Guest Kernel Mapped: 0x60000000 -> 0x80000000 - Guest Usermode virtual memory is limited to 1GB. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | KVM/MIPS32: Infrastructure/build files.Sanjay Lal2013-05-081-1/+5
|/ | | | | | | | | | | | - Add the KVM option to MIPS build files. - Add default config files for KVM host/guest kernels. - Change the link address for the Malta KVM Guest kernel to UM (0x40100000). - Add KVM Kconfig file with KVM/MIPS specific options Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-211-33/+50
|\ | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * MIPS: Add new GIC clocksource.Steven J. Hill2013-02-171-33/+50
| | | | | | | | | | | | | | | | | | Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-0111-47/+47
|/ | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Fix interupt number of CBUS UART.Ralf Baechle2012-11-131-1/+2
| | | | | | | | | | | | | | | | The CBUS UART's interrupt number was wrong conflicting with the interrupt being tied to the Intel PIIX4. Since the PIIX4's interrupt is registered before the CBUS UART which is not being used on most systems this would not be noticed. Attempts to open the ttyS2 CBUS UART would result in: genirq: Flags mismatch irq 18. 00000000 (serial) vs. 00010000 (XT-PIC cascade) serial_link_irq_chain: request failed: -16 for irq: 18 Qemu was written to match the kernel so will need to be fixed also. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'ralf-3.7' of ↵Ralf Baechle2012-09-281-0/+34
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: Make GIC code platform independent.Steven J. Hill2012-09-131-0/+34
| | | | | | | | | | | | | | | | The GIC interrupt code is used by multiple platforms and the current code was half Malta dependent code. These changes abstract away the platform specific differences. Signed-off-by: Steven J. Hill <sjhill@mips.com>
* | Merge branch 'cn68xx-ciu2' of ↵Ralf Baechle2012-09-271-13/+0
|\ \ | | | | | | | | | git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
| * | MIPS: Malta: Delete duplicate PCI fixup.Ralf Baechle2012-08-171-13/+0
| |/ | | | | | | | | | | | | | | | | | | 2ec8663f9c03a96f2c328c7c483603c31d62ad37 (lmo) rsp. 497e5ff03f58583ada469db8a1aa34eced9dd63e (kernel.org) [MIPS: Malta: Move PIIX4 PCI fixup to where it belongs.] attempted to move this PCI fixup but really only added it at it's new location without deleting the old instance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Malta: Don't crash on spurious interrupt.Ralf Baechle2012-09-171-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 48d480b0bde794781fcae9501fb043c1bac0e523 [[MIPS] Malta: Fix off by one bug in interrupt handler.] did not take in account that irq_ffs() will also return 0 if for some reason the set of pending interrupts happens to be empty. This is trivial to trigger with a RM5261 CPU module running a 64-bit kernel and results in something like the following: CPU 0 Unable to handle kernel paging request at virtual address 0000000000000000, epc == ffffffff801772d0, ra == ffffffff8017ad24 Oops[#1]: Cpu 0 $ 0 : 0000000000000000 ffffffff9000a4e0 ffffffff9000a4e0 ffffffff9000a4e0 $ 4 : ffffffff80592be0 0000000000000000 00000000000000d6 ffffffff80322ed0 $ 8 : ffffffff805fe538 0000000000000000 ffffffff9000a4e0 ffffffff80590000 $12 : 00000000000000d6 0000000000000000 ffffffff80600000 ffffffff805fe538 $16 : 0000000000000000 0000000000000010 ffffffff80592be0 0000000000000010 $20 : 0000000000000000 0000000000500001 0000000000000000 ffffffff8051e078 $24 : 0000000000000028 ffffffff803226e8 $28 : 9800000003828000 980000000382b900 ffffffff8051e060 ffffffff8017ad24 Hi : 0000000000000000 Lo : 0000006388974000 epc : ffffffff801772d0 handle_irq_event_percpu+0x70/0x2f0 Not tainted ra : ffffffff8017ad24 handle_percpu_irq+0x54/0x88 Status: 9000a4e2 KX SX UX KERNEL EXL Cause : 00808008 BadVA : 0000000000000000 PrId : 000028a0 (Nevada) Modules linked in: Process init (pid: 1, threadinfo=9800000003828000, task=9800000003827968, tls=0000000077087490) Stack : ffffffff80592be0 ffffffff8058d248 0000000000000040 0000000000000000 ffffffff80613340 0000000000500001 ffffffff805a0000 0000000000000882 9800000003b89000 ffffffff8017ad24 00000000000000d5 0000000000000010 ffffffff9000a4e1 ffffffff801769f4 ffffffff9000a4e0 ffffffff801037f8 0000000000000000 ffffffff80101c44 0000000000000000 ffffffff9000a4e0 0000000000000000 9000000018000000 90000000180003f9 0000000000000001 0000000000000000 00000000000000ff 0000000000000018 0000000000000001 0000000000000001 00000000003fffff 0000000000000020 ffffffff802cf7ac ffffffff80208918 000000007fdadf08 ffffffff80612d88 ffffffff9000a4e1 0000000000000040 0000000000000000 ffffffff80613340 0000000000500001 ... Call Trace: [<ffffffff801772d0>] handle_irq_event_percpu+0x70/0x2f0 [<ffffffff8017ad24>] handle_percpu_irq+0x54/0x88 [<ffffffff801769f4>] generic_handle_irq+0x44/0x60 [<ffffffff801037f8>] do_IRQ+0x48/0x70 [<ffffffff80101c44>] ret_from_irq+0x0/0x4 [<ffffffff80326170>] serial8250_startup+0x310/0x870 [<ffffffff8032175c>] uart_startup.part.7+0x9c/0x330 [<ffffffff80321b4c>] uart_open+0x15c/0x1b0 [<ffffffff80302034>] tty_open+0x1fc/0x720 [<ffffffff801bffac>] chrdev_open+0x7c/0x180 [<ffffffff801b9ab8>] do_dentry_open.isra.14+0x288/0x390 [<ffffffff801bac5c>] nameidata_to_filp+0x5c/0xc0 [<ffffffff801ca700>] do_last.isra.33+0x330/0x8f0 [<ffffffff801caf3c>] path_openat+0xbc/0x440 [<ffffffff801cb3c8>] do_filp_open+0x38/0xa8 [<ffffffff801bade4>] do_sys_open+0x124/0x218 [<ffffffff80110538>] handle_sys+0x118/0x13c Code: 02d5a825 12800012 02a0b02d <de820000> de850008 0040f809 0220202d 0040a82d 40026000 ---[ end trace 5d8e7b9a86badd2d ]--- Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Malta: Remove RTC Data Mode bootstrap breakageMaciej W. Rozycki2012-09-141-5/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | YAMON requires and enforces the RTC Data Mode (Register B, DM bit) to binary, that is the bit is set every time the board goes through the firmware bootstrap sequence. Likewise its calendar manipulation commands interpret or set the RTC registers unconditionally as binary, never actually checking what the value of the DM bit is, under the (correct) assumption that it has been previously set, to indicate the binary mode. A change to Linux a while ago however introduced a platform-specific tweak that clears that bit and therefore forces the data mode to BCD. This causes clock corruption and misinterpretation that has to be fixed up by user-mode tools in system startup scripts as the initial clock is often incorrect according to the BCD interpretation forced. This change removes the hack; a comment included refers to alarm code, but even if it was broken at one point by requiring the BCD mode, it should have been trivially corrected and even if not, given how rarely the alarm feature is used, that was not really a reasonable justification to break the system clock that is indeed used by virtually everything. And either way the alarm code has been since fixed anyway. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PCI: Move fixups from __init to __devinit.Sebastian Andrzej Siewior2012-07-191-1/+1
| | | | | | | | | | | | | | | | Fixups are executed once the pci-device is found which is during boot process so __init seems fine as long as the platform does not support hotplug. However it is possible to remove the PCI bus at run time and have it rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call the fixups again. [ralf@linux-mips.org: Made piixirqmap[] in malta_piix_func0_fixup() __initdata.] Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: mark const init data with __initconst instead of __initdataUwe Kleine-König2012-07-191-1/+1
| | | | | | | | | | | | | | | | | | | As long as there is no other non-const variable marked __initdata in the same compilation unit it doesn't hurt. If there were one however compilation would fail with error: $variablename causes a section type conflict because a section containing const variables is marked read only and so cannot contain non-const variables. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel@pengutronix.de Patchwork: https://patchwork.linux-mips.org/patch/3565/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Change start address to avoid conflicts.Steven J. Hill2012-07-191-2/+3
| | | | | | | | | There are ACPI and SMB devices in the 0x1000..0x1fff address range. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Disintegrate asm/system.h for MIPSDavid Howells2012-03-283-1/+2
| | | | | | | | Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
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