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path: root/arch/mips/mm/tlbex.c
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* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
* MIPS: Add cases for CPU_P5600James Hogan2014-03-261-0/+1
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-061-0/+1
* mips: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-01-241-1/+0
* MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-221-0/+1
* MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-291-82/+87
* MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXTJayachandran C2013-10-291-33/+57
* MIPS: Move definition of SMP processor id register to header fileJayachandran C2013-10-291-50/+6
* MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-171-0/+1
* MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.David Daney2013-08-261-0/+2
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-07-191-2/+2
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| * MIPS: tlbex: fix broken build in v3.11-rc1Aaro Koskinen2013-07-191-1/+1
| * MIPS: tlbex: Fix typo in r3000 tlb store handlerTony Wu2013-07-191-1/+1
* | MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-141-77/+67
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* Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle2013-07-121-14/+42
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| * MIPS: tlbex: Fix size of area to be flushed.Ralf Baechle2013-06-271-1/+1
| * MIPS: Flush TLB handlers directly after writing themJonas Gorski2013-06-251-14/+16
| * MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlersRalf Baechle2013-06-211-0/+26
* | MIPS: Fix typos and cleanup commentTony Wu2013-07-011-1/+1
* | MIPS: Move generated code to .text for microMIPSJayachandran C2013-07-011-40/+44
* | MIPS: Fixup check for invalid scratch registerJayachandran C2013-06-131-5/+5
* | MIPS: Allow platform specific scratch registersJayachandran C2013-06-131-15/+26
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* MIPS: Remove duplicate definition of check_for_high_segbits.David Daney2013-05-231-4/+0
* Revert "MIPS: Allow ASID size to be determined at boot time."David Daney2013-05-161-49/+0
* Revert "MIPS: microMIPS: Support dynamic ASID sizing."David Daney2013-05-161-32/+2
* Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...Ralf Baechle2013-05-091-0/+100
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| * MIPS: microMIPS: Add support for exception handling.Steven J. Hill2013-05-091-0/+21
| * MIPS: microMIPS: Support dynamic ASID sizing.Steven J. Hill2013-05-081-2/+32
| * MIPS: Allow ASID size to be determined at boot time.Steven J. Hill2013-05-081-0/+49
* | Merge branch 'mips-next-3.10' of git://git.linux-mips.org/pub/scm/john/linux-...Ralf Baechle2013-05-081-2/+8
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| * | MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen2013-05-081-2/+8
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* | MIPS: Make declarations and definitions of tlbmiss_handler_setup_pgd match.Ralf Baechle2013-04-111-11/+11
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* Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle2013-02-211-0/+1
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| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-171-0/+1
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-16/+16
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* Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."Ralf Baechle2012-12-271-16/+0
* Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mip...Ralf Baechle2012-12-131-2/+6
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| * MIPS: tlbex: Fix section mismatchesKevin Cernekee2012-11-091-2/+6
* | MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle2012-12-131-18/+0
* | MIPS: Transparent Huge Pages supportRalf Baechle2012-12-121-1/+2
* | MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney2012-12-121-13/+13
* | MIPS: tlbex: Better debug output.Ralf Baechle2012-11-261-13/+55
* | MIPS: Remove R5000A.Ralf Baechle2012-11-261-2/+0
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* MIPS: R5000: Fix TLB hazard handling.Ralf Baechle2012-10-161-15/+8
* MIPS: tlbex: Deal with re-definition of labelRalf Baechle2012-10-161-7/+34
* MIPS: Optimize TLB refill for RI/XI configurations.David Daney2012-10-111-16/+7
* Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...Ralf Baechle2012-09-281-1/+29
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| * MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.Steven J. Hill2012-09-131-0/+16
| * MIPS: Avoid pipeline stalls on some MIPS32R2 cores.Steven J. Hill2012-09-131-1/+13
* | MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-131-7/+7
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