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* [MIPS] Split the micro-assembler from tlbex.c.Thiemo Seufer2008-02-011-1/+2
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-111-1/+1
* [MIPS] Use -Werror on subdirectories which build cleanly.Ralf Baechle2007-07-311-0/+2
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-0/+1
* [MIPS] Kill redundant EXTRA_AFLAGSAtsushi Nemoto2007-02-261-2/+0
* [MIPS] Unify dma-{coherent,noncoherent.ip27,ip32}Ralf Baechle2007-02-131-12/+2
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-291-0/+1
* [MIPS] Kill tlb-andes.c.Thiemo Seufer2006-03-211-1/+1
* Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle2005-10-291-2/+2
* Use R4000 TLB routines for SB1 also.Ralf Baechle2005-10-291-1/+1
* Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle2005-10-291-2/+2
* [PATCH] mips: clean up 32/64-bit configurationRalf Baechle2005-09-051-2/+2
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+44
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