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* MIPS: lantiq: adds code for booting GPHYJohn Crispin2012-11-111-0/+36
| | | | | | | | The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4522
* MIPS: lantiq: fix bootselect bits on XRX200 SoCJohn Crispin2012-11-111-7/+15
| | | | | | | | The XRX200 SoC family has a different register layout for reading the boot selection bits. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4519
* OF: MIPS: lantiq: implement OF supportJohn Crispin2012-05-211-16/+13
| | | | | | | | | | | Activate USE_OF, add a sample DTS file and convert the core soc code to OF. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3803/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: cleanup reset codeJohn Crispin2012-05-151-12/+36
| | | | | | | | | Add 2 new soc specifc handlers and remove superflous pr_notice calls. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix up inconsistency in panic() string argument.Ralf Baechle2011-12-071-3/+3
| | | | | | | | Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: use export.h in favour of module.hJohn Crispin2011-11-141-1/+1
| | | | | | | | | | | The code located at arch/mips/lantiq/ included module.h to be able to use the EXPORT_SYMBOL* macros. These can now be directly included using export.h. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: add SoC specific code for XWAY familyJohn Crispin2011-05-191-0/+91
Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2249/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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