| Commit message (Expand) | Author | Age | Files | Lines |
* | MIPS: smp-cps: cpu_set FPU mask if FPU present | Niklas Cassel | 2015-04-10 | 1 | -0/+6 |
* | MIPS: kernel: entry.S: Set correct ISA level for mips_ihb | Markos Chandras | 2015-04-10 | 1 | -1/+2 |
* | MIPS: unaligned: Fix regular load/store instruction emulation for EVA | Markos Chandras | 2015-04-10 | 1 | -5/+47 |
* | MIPS: unaligned: Surround load/store macros in do {} while statements | Markos Chandras | 2015-04-10 | 1 | -26/+90 |
* | MIPS: unaligned: Prevent EVA instructions on kernel unaligned accesses | Markos Chandras | 2015-04-10 | 1 | -78/+94 |
* | MIPS: Add support for XPA. | Steven J. Hill | 2015-03-19 | 2 | -0/+5 |
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus | Linus Torvalds | 2015-02-21 | 22 | -281/+3598 |
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| * | MIPS: OCTEON: Delete unused COP2 saving code | Aleksey Makarov | 2015-02-20 | 1 | -26/+0 |
| * | MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register | Chandrakala Chavva | 2015-02-20 | 1 | -3/+3 |
| * | MIPS: OCTEON: Save and restore CP2 SHA3 state | David Daney | 2015-02-20 | 2 | -11/+33 |
| * | MIPS: OCTEON: Fix FP context save. | David Daney | 2015-02-20 | 1 | -12/+7 |
| * | MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs | David Daney | 2015-02-20 | 1 | -30/+98 |
| * | MIPS: Add set/clear CP0 macros for PageGrain register | Steven J. Hill | 2015-02-20 | 1 | -1/+1 |
| * | Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/... | Ralf Baechle | 2015-02-19 | 21 | -195/+3334 |
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| | * | MIPS: kernel: elf: Improve the overall ABI and FPU mode checks | Markos Chandras | 2015-02-17 | 1 | -115/+188 |
| | * | MIPS: kernel: process: Do not allow FR=0 on MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -0/+4 |
| | * | MIPS: Make use of the ERETNC instruction on MIPS R6 | Markos Chandras | 2015-02-17 | 3 | -0/+21 |
| | * | MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 | Leonid Yegoshin | 2015-02-17 | 4 | -1/+2407 |
| | * | MIPS: Add LLB bit and related feature for the Config 5 CP0 register | Markos Chandras | 2015-02-17 | 1 | -0/+2 |
| | * | MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions | Markos Chandras | 2015-02-17 | 1 | -0/+10 |
| | * | MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions | Markos Chandras | 2015-02-17 | 1 | -0/+8 |
| | * | MIPS: Emulate the new MIPS R6 BALC instruction | Markos Chandras | 2015-02-17 | 1 | -0/+10 |
| | * | MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions | Markos Chandras | 2015-02-17 | 1 | -1/+5 |
| | * | MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions | Markos Chandras | 2015-02-17 | 1 | -0/+11 |
| | * | MIPS: Emulate the new MIPS R6 branch compact (BC) instruction | Markos Chandras | 2015-02-17 | 1 | -0/+9 |
| | * | MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions | Markos Chandras | 2015-02-17 | 1 | -0/+22 |
| | * | MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions | Markos Chandras | 2015-02-17 | 1 | -0/+31 |
| | * | MIPS: Emulate the BC1{EQ,NE}Z FPU instructions | Markos Chandras | 2015-02-17 | 1 | -29/+72 |
| | * | MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -7/+63 |
| | * | MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -2/+9 |
| | * | MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -1/+1 |
| | * | MIPS: kernel: unaligned: Add support for the MIPS R6 | Leonid Yegoshin | 2015-02-17 | 1 | -4/+386 |
| | * | MIPS: kernel: cps-vec: Replace "addi" with "addiu" | Markos Chandras | 2015-02-17 | 1 | -8/+8 |
| | * | MIPS: kernel: genex: Set correct ISA level | Markos Chandras | 2015-02-17 | 1 | -1/+1 |
| | * | MIPS: kernel: r4k_fpu: Add support for MIPS R6 | Leonid Yegoshin | 2015-02-17 | 1 | -3/+9 |
| | * | MIPS: kernel: r4k_switch: Add support for MIPS R6 | Leonid Yegoshin | 2015-02-17 | 1 | -6/+8 |
| | * | MIPS: kernel: traps: Add MIPS R6 related definitions | Leonid Yegoshin | 2015-02-17 | 1 | -5/+5 |
| | * | MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo | Markos Chandras | 2015-02-17 | 1 | -1/+7 |
| | * | MIPS: kernel: entry.S: Add MIPS R6 related definitions | Markos Chandras | 2015-02-17 | 1 | -2/+3 |
| | * | MIPS: kernel: cpu-probe.c: Add support for MIPS R6 | Leonid Yegoshin | 2015-02-17 | 1 | -4/+16 |
| | * | MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler | Leonid Yegoshin | 2015-02-17 | 1 | -1/+1 |
| | * | MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugs | Leonid Yegoshin | 2015-02-17 | 1 | -4/+7 |
| | * | MIPS: asm: spram: Add new symbol for MIPS scratch pad storage | Markos Chandras | 2015-02-17 | 1 | -1/+1 |
| | * | MIPS: Use generic checksum functions for MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -0/+2 |
| | * | MIPS: Add MIPS generic QEMU probe support | Leonid Yegoshin | 2015-02-16 | 1 | -0/+5 |
| | * | MIPS: Add cases for CPU_QEMU_GENERIC | Leonid Yegoshin | 2015-02-16 | 3 | -0/+3 |
| * | | MIPS: Export MSA functions used by lose_fpu(1) for KVM | James Hogan | 2015-02-19 | 1 | -0/+4 |
| * | | MIPS: Export FP functions used by lose_fpu(1) for KVM | James Hogan | 2015-02-19 | 1 | -0/+6 |
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| * | MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop} | Markos Chandras | 2015-02-16 | 1 | -1/+3 |
| * | MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS | Paul Burton | 2015-02-12 | 2 | -0/+111 |