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* Merge tag 'devicetree-for-3.16' of ↵Linus Torvalds2014-06-041-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next Pull DeviceTree updates from Rob Herring: - Another round of clean-up of FDT related code in architecture code. This removes knowledge of internal FDT details from most architectures except powerpc. - Conversion of kernel's custom FDT parsing code to use libfdt. - DT based initialization for generic serial earlycon. The introduction of generic serial earlycon support went in through the tty tree. - Improve the platform device naming for DT probed devices to ensure unique naming and use parent names instead of a global index. - Fix a race condition in of_update_property. - Unify the various linker section OF match tables and fix several function prototype errors. - Update platform_get_irq_byname to work in deferred probe cases. - 2 binding doc updates * tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits) of: handle NULL node in next_child iterators of/irq: provide more wrappers for !CONFIG_OF devicetree: bindings: Document micrel vendor prefix dt: bindings: dwc2: fix required value for the phy-names property of_pci_irq: kill useless variable in of_irq_parse_pci() of/irq: do irq resolution in platform_get_irq_byname() of: Add a testcase for of_find_node_by_path() of: Make of_find_node_by_path() handle /aliases of: Create unlocked version of for_each_child_of_node() lib: add glibc style strchrnul() variant of: Handle memory@0 node on PPC32 only pci/of: Remove dead code of: fix race between search and remove in of_update_property() of: Use NULL for pointers of: Stop naming platform_device using dcr address of: Ensure unique names without sacrificing determinism tty/serial: pl011: add DT based earlycon support of/fdt: add FDT serial scanning for earlycon of/fdt: add FDT address translation support serial: earlycon: add DT support ...
| * mips: convert fdt pointers to opaque pointersRob Herring2014-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | The architecture code does not need to access the internals of the FDT blob directly, so make the pointers to it void * and use char arrays for section variables. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Tested-by: Grant Likely <grant.likely@linaro.org>
* | Merge branch 'locking-core-for-linus' of ↵Linus Torvalds2014-06-031-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next Pull core locking updates from Ingo Molnar: "The main changes in this cycle were: - reduced/streamlined smp_mb__*() interface that allows more usecases and makes the existing ones less buggy, especially in rarer architectures - add rwsem implementation comments - bump up lockdep limits" * 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (33 commits) rwsem: Add comments to explain the meaning of the rwsem's count field lockdep: Increase static allocations arch: Mass conversion of smp_mb__*() arch,doc: Convert smp_mb__*() arch,xtensa: Convert smp_mb__*() arch,x86: Convert smp_mb__*() arch,tile: Convert smp_mb__*() arch,sparc: Convert smp_mb__*() arch,sh: Convert smp_mb__*() arch,score: Convert smp_mb__*() arch,s390: Convert smp_mb__*() arch,powerpc: Convert smp_mb__*() arch,parisc: Convert smp_mb__*() arch,openrisc: Convert smp_mb__*() arch,mn10300: Convert smp_mb__*() arch,mips: Convert smp_mb__*() arch,metag: Convert smp_mb__*() arch,m68k: Convert smp_mb__*() arch,m32r: Convert smp_mb__*() arch,ia64: Convert smp_mb__*() ...
| * | arch,mips: Convert smp_mb__*()Peter Zijlstra2014-04-181-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS is interesting and has hardware variants that reorder over ll/sc as well as those that do not. Implement the 2 new barrier functions as per the old barriers. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-9ph49jbae3hol9v721sbc2g6@git.kernel.org Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maciej W. Rozycki" <macro@codesourcery.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | MIPS: ptrace: Avoid smp_processor_id() in preemptible codeAlex Smith2014-05-281-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ptrace_{get,set}_watch_regs access current_cpu_data to get the watch register count/masks, which calls smp_processor_id(). However they are run in preemptible context and therefore trigger warnings like so: [ 6340.092000] BUG: using smp_processor_id() in preemptible [00000000] code: gdb/367 [ 6340.092000] caller is ptrace_get_watch_regs+0x44/0x220 Since the watch register count/masks should be the same across all CPUs, use boot_cpu_data instead. Note that this may need to change in future should a heterogenous system be supported where the count/masks are not the same across all CPUs (the current code is also incorrect for this scenario - current_cpu_data here would not necessarily be correct for the CPU that the target task will execute on). Signed-off-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6879/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Fix typo when reporting cache and ftlb errors for ImgTec coresMarkos Chandras2014-05-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduced by the following two commits: 75b5b5e0a262790fa11043fe45700499c7e3d818 "MIPS: Add support for FTLBs" 6de20451857ed14a4eecc28d08f6de5925d1cf96 "MIPS: Add printing of ES bit for Imgtec cores when cache error occurs" Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reported-by: Matheus Almeida <Matheus.Almeida@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: stable@vger.kernel.org # v3.14+ Patchwork: https://patchwork.linux-mips.org/patch/6980/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Fix branch emulation of branch likely instructions.Ralf Baechle2014-05-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two issues: o For beql_op, beql_op, bne_op, bnel_op, blez_op, blezl_op, bgtz_op and bgtzl_op the wrong field was being checked for the instruction opcode. o For blez_op / blezl_op and bgtz_op / bgtzl_op the test was testing for the wrong opcode. This bug got introduced by d8d4e3ae0b5c179c0bfd3f0af5b352d13bea9cfa [MIPS Kprobes: Refactor branch emulation]. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Acked-by: Victor Kamensky <kamensky@cisco.com>
* | MIPS: Wire up renameat2 syscall.Ralf Baechle2014-05-134-0/+4
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Revert "MIPS: MT: proc: Add support for printing VPE and TC ids"Ralf Baechle2014-05-131-8/+1
|/ | | | | | | Reverts commit 795038a6910937fa167d47f6f6183db0eb8fb706 because d6d3c9afaab47418ab2d7f874fb8aeac1f067104 provides the same functionality in a more generic way. Both patches applied however means that the VPE and TC IDs get printed twice currently.
* Merge git://git.infradead.org/users/eparis/auditLinus Torvalds2014-04-121-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull audit updates from Eric Paris. * git://git.infradead.org/users/eparis/audit: (28 commits) AUDIT: make audit_is_compat depend on CONFIG_AUDIT_COMPAT_GENERIC audit: renumber AUDIT_FEATURE_CHANGE into the 1300 range audit: do not cast audit_rule_data pointers pointlesly AUDIT: Allow login in non-init namespaces audit: define audit_is_compat in kernel internal header kernel: Use RCU_INIT_POINTER(x, NULL) in audit.c sched: declare pid_alive as inline audit: use uapi/linux/audit.h for AUDIT_ARCH declarations syscall_get_arch: remove useless function arguments audit: remove stray newline from audit_log_execve_info() audit_panic() call audit: remove stray newlines from audit_log_lost messages audit: include subject in login records audit: remove superfluous new- prefix in AUDIT_LOGIN messages audit: allow user processes to log from another PID namespace audit: anchor all pid references in the initial pid namespace audit: convert PPIDs to the inital PID namespace. pid: get pid_t ppid of task in init_pid_ns audit: rename the misleading audit_get_context() to audit_take_context() audit: Add generic compat syscall support audit: Add CONFIG_HAVE_ARCH_AUDITSYSCALL ...
| * syscall_get_arch: remove useless function argumentsEric Paris2014-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every caller of syscall_get_arch() uses current for the task and no implementors of the function need args. So just get rid of both of those things. Admittedly, since these are inline functions we aren't wasting stack space, but it just makes the prototypes better. Signed-off-by: Eric Paris <eparis@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: linux390@de.ibm.com Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-s390@vger.kernel.org Cc: linux-arch@vger.kernel.org
* | Merge tag 'trace-3.15' of ↵Linus Torvalds2014-04-031-4/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace Pull tracing updates from Steven Rostedt: "Most of the changes were largely clean ups, and some documentation. But there were a few features that were added: Uprobes now work with event triggers and multi buffers and have support under ftrace and perf. The big feature is that the function tracer can now be used within the multi buffer instances. That is, you can now trace some functions in one buffer, others in another buffer, all functions in a third buffer and so on. They are basically agnostic from each other. This only works for the function tracer and not for the function graph trace, although you can have the function graph tracer running in the top level buffer (or any tracer for that matter) and have different function tracing going on in the sub buffers" * tag 'trace-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: (45 commits) tracing: Add BUG_ON when stack end location is over written tracepoint: Remove unused API functions Revert "tracing: Move event storage for array from macro to standalone function" ftrace: Constify ftrace_text_reserved tracepoints: API doc update to tracepoint_probe_register() return value tracepoints: API doc update to data argument ftrace: Fix compilation warning about control_ops_free ftrace/x86: BUG when ftrace recovery fails ftrace: Warn on error when modifying ftrace function ftrace: Remove freelist from struct dyn_ftrace ftrace: Do not pass data to ftrace_dyn_arch_init ftrace: Pass retval through return in ftrace_dyn_arch_init() ftrace: Inline the code from ftrace_dyn_table_alloc() ftrace: Cleanup of global variables ftrace_new_pgs and ftrace_update_cnt tracing: Evaluate len expression only once in __dynamic_array macro tracing: Correctly expand len expressions from __dynamic_array macro tracing/module: Replace include of tracepoint.h with jump_label.h in module.h tracing: Fix event header migrate.h to include tracepoint.h tracing: Fix event header writeback.h to include tracepoint.h tracing: Warn if a tracepoint is not set via debugfs ...
| * | ftrace: Do not pass data to ftrace_dyn_arch_initJiri Slaby2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the data parameter is not really used by any ftrace_dyn_arch_init, remove that from ftrace_dyn_arch_init. This also removes the addr local variable from ftrace_init which is now unused. Note the documentation was imprecise as it did not suggest to set (*data) to 0. Link: http://lkml.kernel.org/r/1393268401-24379-4-git-send-email-jslaby@suse.cz Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-arch@vger.kernel.org Signed-off-by: Jiri Slaby <jslaby@suse.cz> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
| * | ftrace: Pass retval through return in ftrace_dyn_arch_init()Jiri Slaby2014-03-071-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No architecture uses the "data" parameter in ftrace_dyn_arch_init() in any way, it just sets the value to 0. And this is used as a return value in the caller -- ftrace_init, which just checks the retval against zero. Note there is also "return 0" in every ftrace_dyn_arch_init. So it is enough to check the retval and remove all the indirect sets of data on all archs. Link: http://lkml.kernel.org/r/1393268401-24379-3-git-send-email-jslaby@suse.cz Cc: linux-arch@vger.kernel.org Signed-off-by: Jiri Slaby <jslaby@suse.cz> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
* | | Merge branch 'mips-for-linux-next' of ↵Linus Torvalds2014-04-0236-371/+2010
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/ralf/upstream-sfr Pull MIPS updates from Ralf Baechle: - Support for Imgtec's Aptiv family of MIPS cores. - Improved detection of BCM47xx configurations. - Fix hiberation for certain configurations. - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and systems. - Detection and support for the MIPS P5600 core. - A few more random fixes that didn't make 3.14. - Support for the EVA Extended Virtual Addressing - Switch Alchemy to the platform PATA driver - Complete unification of Alchemy support - Allow availability of I/O cache coherency to be runtime detected - Improvments to multiprocessing support for Imgtec platforms - A few microoptimizations - Cleanups of FPU support - Paul Gortmaker's fixes for the init stuff - Support for seccomp * 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits) MIPS: CPC: Use __raw_ memory access functions MIPS: CM: use __raw_ memory access functions MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n MIPS: Malta: GIC IPIs may be used without MT MIPS: smp-mt: Use common GIC IPI implementation MIPS: smp-cmp: Remove incorrect core number probe MIPS: Fix gigaton of warning building with microMIPS. MIPS: Fix core number detection for MT cores MIPS: MT: core_nvpes function to retrieve VPE count MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n MIPS: Lasat: Replace del_timer by del_timer_sync MIPS: Malta: Setup PM I/O region on boot MIPS: Loongson: Add a Loongson-3 default config file MIPS: Loongson 3: Add CPU hotplug support MIPS: Loongson 3: Add Loongson-3 SMP support MIPS: Loongson: Add Loongson-3 Kconfig options MIPS: Loongson: Add swiotlb to support All-Memory DMA MIPS: Loongson 3: Add serial port support MIPS: Loongson 3: Add IRQ init and dispatch support MIPS: Loongson 3: Add HT-linked PCI support ...
| * \ \ Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2014-03-314-11/+16
| |\ \ \
| * | | | MIPS: smp-mt: Use common GIC IPI implementationPaul Burton2014-03-311-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than duplicating the GIC IPI send function, share the one already used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6653/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: smp-cmp: Remove incorrect core number probePaul Burton2014-03-311-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This probing is already done by decode_configs as part of cpu_probe, and furthermore the implementation here was incorrect for any MT core with a number of VPEs other than 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Fix gigaton of warning building with microMIPS.Ralf Baechle2014-03-316-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Fix core number detection for MT coresPaul Burton2014-03-311-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In cores which implement the MT ASE, the CPUNum in the EBase register is a concatenation of the core number & the VPE ID within that core. In order to retrieve the correct core number CPUNum must be shifted appropriately to remove the VPE ID bits. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen2014-03-311-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle2014-03-313-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
| * | | | MIPS: Simplify ptrace_getfpregs FPU IR retrievalPaul Burton2014-03-311-24/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6147/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Simplify PTRACE_PEEKUSR for FPC_EIRPaul Burton2014-03-312-76/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6144/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin2014-03-311-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2Huacai Chen2014-03-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen <chenhc@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: perf: Add interAptiv supportDeng-Cheng Zhu2014-03-311-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: perf: Add proAptiv supportDeng-Cheng Zhu2014-03-311-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Choose event/cache maps and handle raw event mapping for proAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv supportDeng-Cheng Zhu2014-03-311-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6526/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: cpu-probe: Add support for probing M5150 coresLeonid Yegoshin2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6597/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: malta: Add support for SMP EVAMarkos Chandras2014-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: proc: Add EVA to the list of CPU featuresMarkos Chandras2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: cpu-probe: Enable EVA option on supported coresMarkos Chandras2014-03-261-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushesLeonid Yegoshin2014-03-262-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When flushing the icache, make sure the address limit is correct so the appropriate 'cache' instruction will be used. This has no impact on cores operating in non-eva mode. However, when EVA is enabled, we ensure that 'cache' will be used instead of 'cachee'. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: signal: Prevent save/restore FPU context in user memoryLeonid Yegoshin2014-03-261-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EVA does not have FPU specific instructions for reading or writing FPU registers from userspace memory. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: checksum: Split the 'copy_user' symbolMarkos Chandras2014-03-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'copy_user' symbol can be used to copy from or to userland so we will use two different symbols for these operations. This makes no difference in the existing code, but when the core is operating in EVA mode, different instructions need to be used to read and write to userland address space. The old function has also been renamed to 'copy_kernel' to denote that it is suitable for copy data to and from kernel space. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: unaligned: Handle unaligned accesses for EVALeonid Yegoshin2014-03-261-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle unaligned accesses when we access userspace memory EVA mode. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: unaligned: Add EVA instruction wrappersMarkos Chandras2014-03-261-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the load/store instruction wrappers from asm/asm.h to perform such operations when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: lib: memcpy: Add EVA supportMarkos Chandras2014-03-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add copy_{to,from,in}_user when the CPU operates in EVA mode. This is necessary so the EVA specific instructions can be used to perform the virtual to physical translation for user space addresses. We will use the non-EVA functions to read from kernel if needed. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: lib: strncpy_user: Add EVA supportMarkos Chandras2014-03-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In non-EVA mode, strncpy_from_user* aliases are used for the strncpy_from_kernel* symbols since the code is identical. In EVA mode, new strcpy_from_user* symbols are used which use the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: lib: strlen_user: Add EVA supportMarkos Chandras2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In non-EVA mode, strlen_user* aliases are used for the strlen_kernel* symbols since the code is identical. In EVA mode, new strlen_user* symbols are used which use the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: lib: strnlen_user: Add EVA supportMarkos Chandras2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In non-EVA mode, a strlen_user* alias is used for the strlen_kernel* symbols since the code is identical. In EVA mode, a new strlen_user* symbol is used which uses the EVA specific instructions to load values from userspace. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: traps: Set correct address limit for breakpoints and trapsLeonid Yegoshin2014-03-261-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: traps: Whitespace clean upMarkos Chandras2014-03-261-7/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: kernel: scall32-o32: Use EVA wrappers to fetch syscall argumentsMarkos Chandras2014-03-261-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arguments 4-8 are stored on user's stack, so use the EVA instructions to fetch them if EVA is enabled. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | | | MIPS: Allow FTLB to be turned on for CPU_P5600James Hogan2014-03-261-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow FTLB to be turned on or off for CPU_P5600 as well as CPU_PROAPTIV. The existing if statement is converted into a switch to allow for future expansion. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6411/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Add MIPS P5600 probe supportJames Hogan2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a case in cpu_probe_mips for the MIPS P5600 processor ID, which sets the CPU type to the new CPU_P5600. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6409/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Add cases for CPU_P5600James Hogan2014-03-263-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | MIPS: Save/restore MSA context around signalsPaul Burton2014-03-264-16/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends sigcontext in order to hold the most significant 64 bits of each vector register in addition to the MSA control & status register. The least significant 64 bits are already saved as the scalar FP context. This makes things a little awkward since the least & most significant 64 bits of each vector register are not contiguous in memory. Thus the copy_u & insert instructions are used to transfer the values of the most significant 64 bits via GP registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6533/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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