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* MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platformsRalf Baechle2009-03-301-1/+2
| | | | | | __do_IRQ() is deprecated and will go away. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.Ralf Baechle2007-11-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use name instead of typename for each irq_chipAtsushi Nemoto2007-02-061-2/+2
| | | | | | | The "typename" field was obsoleted by the "name" field. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto2007-02-061-10/+7
| | | | | | | | | | | | | | | | | | | | | | The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Compile __do_IRQ() when really neededFranck Bui-Huu2006-12-061-10/+0
| | | | | | | | | | | | | | | | | __do_IRQ() is needed only by irq handlers that can't use default handlers defined in kernel/irq/chip.c. For others platforms there's no need to compile this function since it won't be used. For those platforms this patch defines GENERIC_HARDIRQS_NO__DO_IRQ symbol which is used exactly for this purpose. Futhermore for platforms which do not use __do_IRQ(), end() method which is part of the 'irq_chip' structure is not used. This patch simply removes this method in this case. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto2006-11-301-1/+4
| | | | | | | | | | | | | | Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IRQ cleanupsAtsushi Nemoto2006-11-301-64/+13
| | | | | | | | | | | | | | | | | | | | | This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Eleminate interrupt migration helper use.Ralf Baechle2006-07-131-2/+2
| | | | | | | | | > #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] genirq: rename desc->handler to desc->chipIngo Molnar2006-06-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* MT bulletproofing.Ralf Baechle2005-10-291-12/+67
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Inlining will result in back-to-back mtc0 mfc0 instructions. Break theRalf Baechle2005-10-291-0/+2
| | | | | | hazard by using back_to_back_c0_hazard(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use an irq_enable_hazard hazard barrier in unmask_mips_irq. ThisRalf Baechle2005-10-291-0/+2
| | | | | | | | | hasn't been an actual bug, so it's more a change to be 100% compliant with the requirements of the architecture spec. Similar fix to mask_mips_irq where there was a slightly less theoretical chance of getting hit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Convert struct hw_interrupt_type initializations to ISO C99 namedRalf Baechle2005-10-291-8/+7
| | | | | | initializers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Mask and ack CPU interrupts upon initialization. Keep the stateMaciej W. Rozycki2005-10-291-1/+6
| | | | | | of software interrupts when unmasking. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+118
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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