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* MIPS: seccomp: Handle indirect system calls (o32)Markos Chandras2014-03-262-2/+20
| | | | | | | | | | | | | | | | | | | When userland uses syscall() to perform an indirect system call the actually system call that needs to be checked by the filter is on the first argument. The kernel code needs to handle this case by looking at the original syscall number in v0 and if it's NR_syscall, then it needs to examine the first argument to identify the real system call that will be executed. Similarly, we need to 'virtually' shift the syscall() arguments so the syscall_get_arguments() function can fetch the correct arguments for the indirect system call. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6404/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ptrace: Move away from secure_computing_strictMarkos Chandras2014-03-261-1/+1
| | | | | | | | | | | | MIPS now has the infrastructure for dynamic seccomp-bpf filtering Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6400/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: thread_info: Add _TIF_SECCOMP flagMarkos Chandras2014-03-261-1/+2
| | | | | | | | | | | | Add _TIF_SECCOMP flag to _TIF_WORK_SYSCALL_ENTRY to indicate that the system call needs to be checked against a seccomp filter. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6405/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: syscall: Define syscall_get_archMarkos Chandras2014-03-261-2/+4
| | | | | | | | | | | | | | | | | | | This effectively renames __syscall_get_arch to syscall_get_arch and implements a compatible interface for the seccomp API. The seccomp code (kernel/seccomp.c) expects a syscall_get_arch function to be defined for every architecture, so we drop the leading underscores from the existing function. This also makes use of the 'task' argument to determine the type the process instead of assuming the process has the same characteristics as the kernel it's running on. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6398/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: syscall: Add the syscall_rollback functionMarkos Chandras2014-03-261-0/+6
| | | | | | | | | | | | | The syscall_rollback function is used by seccomp-bpf but it was never added for MIPS. It doesn't need to do anything as none of the registers are clobbered if the system call has been denied by the seccomp filter. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6403/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove gcmpregs.hPaul Burton2014-03-261-125/+0
| | | | | | | | | | | This header was used only by Malta but is used no longer. Remove it. It was also included unnecessarily in irq-gic.c, so that include is also removed. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6366/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Probe CPC when supportedPaul Burton2014-03-261-0/+5
| | | | | | | | | | | When CPC support is compiled into the kernel (ie. CONFIG_MIPS_CPC=y), probe the CPC on boot for Malta in order to allow any users of the CPC to detect its presence & function correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6363/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Make use of generic CM supportPaul Burton2014-03-261-0/+5
| | | | | | | | | | Remove the Malta-specific CM probe code and instead make use of the newly added generic CM code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6364/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Coherent Processing System SMP implementationPaul Burton2014-03-262-0/+42
| | | | | | | | | | | | | | | | | | This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add cpu_vpe_id macroPaul Burton2014-03-261-0/+6
| | | | | | | | | | | | | The vpe_id field of struct cpuinfo_mips is only present when one of CONFIG_MIPS_MT_{SMP,SMTC} is enabled. That means that any code accessing which may compile without MT is currently forced to use an #ifdef. Instead this patch provides an accessor macro, #ifdef'd appropriately to prevent further #ifdef's elsewhere. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6646/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CPC probe, access functionsPaul Burton2014-03-061-0/+150
| | | | | | | | | | | This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add generic CM probe & access codePaul Burton2014-03-061-0/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move GIC IPI functions out of smp-cmp.cPaul Burton2014-03-061-0/+3
| | | | | | | | | | | | | The GIC IPI functions aren't necessarily specific to the "CMP framework" SMP implementation, and will be used elsewhere in a subsequent commit. This patch adds cleaned up GIC IPI functions to a separate file which is compiled when a new CONFIG_MIPS_GIC_IPI Kconfig symbol is selected, and selects that symbol for CONFIG_MIPS_CMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6359/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Introduce _EXT assembler macroPaul Burton2014-03-061-0/+11
| | | | | | | | | | | This patch adds a simple macro to wrap the ext instruction which was introduced with MIPSR2, and fall back to a shift & and pair for pre-MIPSR2 CPUs. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6358/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add missing includes to gic.hPaul Burton2014-03-061-0/+3
| | | | | | | | | | | | The gic.h header uses bitmaps and NR_CPUS, and should therefore include linux/bitmap.h and linux/threads.h. This is in preparation for use of this header in a subsequent commit from a C file which doesn't already include those headers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6357/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CP0 CMGCRBase definitions & accessorPaul Burton2014-03-061-0/+6
| | | | | | | | | | | | | The CMGCRBase register is defined by the PRA specification as an optional register which indicates the physical base of the MIPS Coherence Manager Global Control Register block. This patch simply adds a definition for the base address field within the register, along with an accessor function for reading the register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6356/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define Config1 cache field shifts & sizesPaul Burton2014-03-061-0/+12
| | | | | | | | | | These fields will be used from assembly code in a subsequent commit, and defining the size & offset of each field makes that use easier. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-061-1/+1
| | | | | | | | | | | | The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras2014-03-061-0/+3
| | | | | | | | | | | | | The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: fpu.h: Fix build when CONFIG_BUG is not setAaro Koskinen2014-02-061-0/+2
| | | | | | | | | | | | | | | | | __enable_fpu produces a build failure when CONFIG_BUG is not set: In file included from arch/mips/kernel/cpu-probe.c:24:0: arch/mips/include/asm/fpu.h: In function '__enable_fpu': arch/mips/include/asm/fpu.h:77:1: error: control reaches end of non-void function [-Werror=return-type] This is regression introduced in 3.14-rc1. Fix that. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Paul Burton <paul.burton@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6504/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Wire up sched_setattr/sched_getattr syscallsJames Hogan2014-02-041-6/+12
| | | | | | | | | | | | | Wire up for MIPS the new sched_setattr and sched_getattr system calls added in commit d50dde5a10f3 (sched: Add new scheduler syscalls to support an extended scheduling parameters ABI) merged in v3.14-rc1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6502/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-01-3050-469/+979
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
| * mips: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-01-244-4/+0
| | | | | | | | | | | | | | | | | | | | | | None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6320/
| * MIPS: KVM: remove shadow_tlb codeJames Hogan2014-01-241-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kvm_mips_init_shadow_tlb() function is called from kvm_arch_vcpu_init() and initialises entries 0 to current_cpu_data.tlbsize-1 of the virtual cpu's shadow_tlb[64] array. However newer cores with FTLBs can have a tlbsize > 64, for example the ProAptiv I'm testing on has a total tlbsize of 576. This causes kvm_mips_init_shadow_tlb() to overflow the shadow_tlb[64] array and overwrite the comparecount_timer among other things, causing a lock up when starting a KVM guest. Aside from kvm_mips_init_shadow_tlb() which only initialises it, the shadow_tlb[64] array is only actually used by the following functions: - kvm_shadow_tlb_put() & kvm_shadow_tlb_load() These are never called. The only call sites are #if 0'd out. - kvm_mips_dump_shadow_tlbs() This is never called. It was originally added for trap & emulate, but turned out to be unnecessary so it was disabled. So instead of fixing the shadow_tlb initialisation code, lets just remove the shadow_tlb[64] array and the above functions entirely. The only functional change here is the removal of broken shadow_tlb initialisation. The rest just deletes dead code. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Gleb Natapov <gleb@redhat.com> Cc: kvm@vger.kernel.org Cc: Sanjay Lal <sanjayl@kymasys.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6384/
| * mips/ide: flush dcache also if icache does not snoop dcacheSebastian Andrzej Siewior2014-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If this is not done then the new just read data which remains in dcache will not make it into icache on time. Thus the CPU loads invalid data and executes crap. The result is that the user is not able to execute anything from its IDE based media while reading plain data is still working well. This problem has been reported as Debian #404951 http://bugs.debian.org/404951 http://comments.gmane.org/gmane.linux.ide/45092 Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/2820/
| * MIPS: BCM47XX: add board detection for Linksys WRT54GS V1Hauke Mehrtens2014-01-241-0/+1
| | | | | | | | | | | | | | | | | | This adds board detection for Linksys WRT54GS V1. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6317/
| * MIPS: Netlogic: Remove XLR early serial setupJayachandran C2014-01-241-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early serial code is not needed because we already have early printk support provided by common/earlycons.c This change also fixes the following build error that occurs when CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards: arch/mips/built-in.o: In function `nlm_early_serial_setup': setup.c:(.init.text+0x274): undefined reference to `early_serial_setup' make: *** [vmlinux] Error 1 Reported-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6083/
| * MIPS: Netlogic: XLP9XX USB supportGanesan Ramalingam2014-01-242-0/+5
| | | | | | | | | | | | | | | | | | | | | | XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB block is similar to the one on XLP2XX, so update usb-init-xlp2.c to handle XLP9XX as well. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6285/
| * MIPS: PCI: Netlogic XLP9XX supportJayachandran C2014-01-242-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add PCI support for Netlogic XLP9XX. The PCI registers and SoC bus numbers have changed in XLP9XX. Also skip a few (bus,dev,fn) combinations which have issues when read. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6284/
| * MIPS: Netlogic: Add cpu to node mapping for XLP9XXJayachandran C2014-01-242-3/+15
| | | | | | | | | | | | | | | | | | XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX. Update code that calculates node id from cpu id to handle this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6283/
| * MIPS: Netlogic: XLP9XX bridge and DRAM codeJayachandran C2014-01-241-37/+32
| | | | | | | | | | | | | | | | | | Update bridge code. Add code to the XLP9XX registers for DRAM size, limit and node when running on XLPXX Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6282/
| * MIPS: Netlogic: XLP9XX UART offsetJayachandran C2014-01-241-1/+2
| | | | | | | | | | | | | | | | Update IO offset of the early console UART. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6281/
| * MIPS: Netlogic: SYS block updates of XLP9XXJayachandran C2014-01-241-1/+17
| | | | | | | | | | | | | | | | | | | | Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6280/
| * MIPS: Netlogic: XLP9XX PIC updatesJayachandran C2014-01-241-24/+48
| | | | | | | | | | | | | | | | | | Functions for the XLP9XX interrupt table entry format and other PIC register changes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6279/
| * MIPS: Netlogic: update iomap.h for XLP9XXJayachandran C2014-01-242-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | Most IO block offsets have changed in XLP9XX. Update iomap.h to add the new addresses of different SoC blocks like PIC, SYS, UART etc. that are needed by the base code. On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus corresponding to the node. Update iomap code to reflect this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6277/
| * MIPS: Netlogic: Identify XLP 9XX chipJayachandran C2014-01-242-1/+9
| | | | | | | | | | | | | | | | | | Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6274/
| * MIPS: Netlogic: Add macro for node presentJayachandran C2014-01-241-0/+2
| | | | | | | | | | | | | | | | | | Add macro nlm_node_present() that can be used to check if a node is present in a multi-chip configuration. This can be used even when NUMA is not enabled. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6272/
| * MIPS: Netlogic: Add topology.h for XLP familyJayachandran C2014-01-243-18/+39
| | | | | | | | | | | | | | | | | | Add mach-netlogic/topology.h which contains XLP cpu number to core and node mapping. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6271/
| * MIPS: Netlogic: Add MSI support for XLPJayachandran C2014-01-245-18/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
| * MIPS: jz4740: update platform data for JZ4740 usb device controllerApelete Seketeli2014-01-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform data already available in tree for JZ4740 USB Device Controller was previously used by an out-of-tree USB gadget driver which was not relying on the musb driver and was written by Ingenic and the Qi-Hardware community. Update platform data for JZ4740 USB device controller to be used with musb driver. Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6265/
| * MIPS: clean up resume declarationPaul Burton2014-01-241-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up the declaration of the resume function by replacing void pointers with their correct types. The irrelevant & incorrect comment preceeding the resume function is replaced by one documenting its function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6146/
| * MIPS: include linux/types.hQais Yousef2014-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6212/
| * MIPS: BCM63XX: use linux/serial_bcm63xx.hFlorian Fainelli2014-01-231-7/+0
| | | | | | | | | | | | | | | | | | | | | | Update the early_printk code to include linux/serial_bcm63xx.h which provides the definitions for the UART block registers. While at it, remove the inclusion of serial_bcm63xx.h which was just there to allow smooth transition. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6203/
| * MIPS: BCM63XX: move UART register definitionsFlorian Fainelli2014-01-231-114/+1
| | | | | | | | | | | | | | | | | | | | Move the BCM63XX UART driver definitions to include/linux/serial_bcm63xx.h such that we do not rely on the MIPS BCM63XX code to provide these for us. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6202/
| * MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.David Daney2014-01-231-0/+9
| | | | | | | | | | | | | | | | | | | | This will be needed by the next patch to use said nodes for probing via the device tree. Signed-off-by: David Daney <david.daney@cavium.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6185/
| * MIPS: Malta: mux & enable SERIRQ interruptPaul Burton2014-01-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
| * MIPS: Fix build error seen in some configurationsGuenter Roeck2014-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following build error is seen if CONFIG_32BIT is undefined, CONFIG_64BIT is defined, and CONFIG_MIPS32_O32 is undefined. asm/syscall.h: In function 'mips_get_syscall_arg': arch/mips/include/asm/syscall.h:32:16: error: unused variable 'usp' [-Werror=unused-variable] cc1: all warnings being treated as errors Fixes: c0ff3c53d4f9 ('MIPS: Enable HAVE_ARCH_TRACEHOOK') Signed-off-by: Guenter Roeck <linux@roeck-us.net> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6160/
| * MIPS: improve checks for noncoherent DMAFelix Fietkau2014-01-222-4/+9
| | | | | | | | | | | | | | | | | | | | | | Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
| * MIPS: APRP: Code formatting clean-ups.Steven J. Hill2014-01-223-21/+18
| | | | | | | | | | | | | | | | | | Clean-up code according to the 'checkpatch.pl' script. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/ Reviewed-by: John Crispin <blogic@openwrt.org>
| * MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu2014-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6096/
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