| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | MIPS: Octeon: Update register definitions for CN63XX chips | David Daney | 2010-10-29 | 1 | -27/+14 |
| | | | | | | | | | | | | The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | ||||
| * | MIPS: Add Cavium OCTEON processor CSR definitions | David Daney | 2009-01-11 | 1 | -0/+240 |
| Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | |||||
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index : op-kernel-dev | |
| Development kernel branch for OpenPOWER systems | Raptor Engineering, LLC |
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