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* MIPS: CM: Add support for reporting CM cache errorsMarkos Chandras2015-08-261-0/+9
| | | | | | | | | | | | The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10646/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mips-cm: Extend CM accessors for 64-bit CPUsMarkos Chandras2015-08-261-4/+44
| | | | | | | | | | | | | | | | | | Previously, the CM accessors were only accessing CM registers as u32 types instead of using the native CM register with. However, newer CMs may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs (CM3) hold all the useful configuration bits in the lower half of the 64-bit registers (at least most of them) so they can still be accessed using the current 32-bit accessors. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: Add GCR_L2_CONFIG register accessorsPaul Burton2015-08-261-0/+11
| | | | | | | | | | | Provide accessor functions for the GCR_L2_CONFIG register introduced with CM3, and define the bits included in the register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mips-cm: Implement mips_cm_revisionPaul Burton2015-08-261-0/+21
| | | | | | | | | | | | | | Provide a function to trivially return the version of the CM present in the system, or 0 if no CM is present. The mips_cm_revision() will be used later on to determine the CM register width, so it must not use the regular CM accessors to read the revision register since that will lead to build failures due to recursive inlines. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10655/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: include errno.h for ENODEV in mips-cm.hPaul Burton2015-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | A later patch in this series will include mips-cm.h but does not require errno.h. This leads to a build failure with ENODEV undeclared. Include errno.h from mips-cm.h to pull in the appropriate definition and avoid the build failure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define GCR_GIC_STATUS register fieldsPaul Burton2015-06-211-0/+4
| | | | | | | | | | | | | | | | | | Add definitions for the GICEX field in the GCR_GIC_STATUS register to mips-cm.h for use in a later patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/10112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mips-cm: Fix sparse warningsJames Hogan2015-01-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Sparse emits a bunch of warnings in mips-cm.h due to casting away of __iomem by the addr_gcr_*() functions: arch/mips/include/asm/mips-cm.h:134:1: warning: cast removes address space of expression And subsequent passing of the return values to __raw_readl() and __raw_writel() in the read_gcr_*() and write_gcr_*() functions: arch/mips/include/asm/mips-cm.h:134:1: warning: incorrect type in argument 2 (different address spaces) arch/mips/include/asm/mips-cm.h:134:1: expected void volatile [noderef] <asn:2>*mem arch/mips/include/asm/mips-cm.h:134:1: got unsigned int [usertype] * arch/mips/include/asm/mips-cm.h:134:1: warning: incorrect type in argument 1 (different address spaces) arch/mips/include/asm/mips-cm.h:134:1: expected void const volatile [noderef] <asn:2>*mem arch/mips/include/asm/mips-cm.h:134:1: got unsigned int [usertype] * Fix by adding __iomem to the addr_gcr_*() return type and cast. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace use of phys_t with phys_addr_t.Ralf Baechle2014-11-241-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: use __raw_ memory access functionsPaul Burton2014-03-311-2/+2
| | | | | | | | | | | The CM registers use native endianness, so using plain readl & writel will produce incorrect results on big endian systems. Reported-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6656/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add generic CM probe & access codePaul Burton2014-03-061-0/+322
The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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