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* MIPS: cpu-probe: Set the write-combine CCA value on per core basisMarkos Chandras2014-09-221-0/+5
| | | | | | | | | | | | Different cores use different CCA values to achieve write-combine memory writes. For cores that do not support write-combine we set the default value to CCA:2 (uncached, non-coherent) which is the default value as set by the kernel. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7402/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu-info: Change the cpu options variable to unsigned long longMarkos Chandras2014-08-021-1/+1
| | | | | | | | | | | | | | | Long integers which are 4 bytes in MIPS32 can't hold new CPU options anymore, so the type of the 'options' variable is changed to unsigned long long which allows 32 more cpu options to be defined for MIPS32 Also, re-arrange the 'options' struct member to avoid potential 4-byte alignment gap in the middle of the struct. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7324/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support CPU topology files in sysfsHuacai Chen2014-07-301-0/+1
| | | | | | | | | | | | | | | | | This patch is prepared for Loongson's NUMA support, it offer meaningful sysfs files such as physical_package_id, core_id, core_siblings and thread_siblings in /sys/devices/system/cpu/cpu?/topology. Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7184/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix potential build failures using cpu_vpe_id on non-MTPaul Burton2014-07-301-1/+1
| | | | | | | | | | | | | | | When used in a non-MT kernel, the cpu_vpe_id macro never made use of its cpuinfo argument. It doesn't actually need to since it is returning a constant 0. However not using the argument can lead to build failures if the compiler then notices that a variable used as part of the argument is unused. Prevent that problem by "using" the argument as far as the compiler is concerned, whilst still returning 0 as before. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7280/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.15-fixes' into mips-for-linux-nextRalf Baechle2014-06-041-2/+2
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| * MIPS: Change type of asid_cache to unsigned longRalf Baechle2014-05-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | asid_cache must be unsigned long otherwise on 64 bit systems it will become 0 if the value in get_new_mmu_context() reaches 0xffffffff and in the end the assumption of ASID_FIRST_VERSION is not true anymore thus leads to more dangerous things. Initial patch by Yong Zhang <yong.zhang@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: libin <huawei.libin@huawei.com>
* | MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-9/+4
|/ | | | | | | | | | | | | | | Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle2014-03-311-0/+21
| | | | | | | | | | | | | | And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
* MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+1
| | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add cpu_vpe_id macroPaul Burton2014-03-261-0/+6
| | | | | | | | | | | | | The vpe_id field of struct cpuinfo_mips is only present when one of CONFIG_MIPS_MT_{SMP,SMTC} is enabled. That means that any code accessing which may compile without MT is currently forced to use an #ifdef. Instead this patch provides an accessor macro, #ifdef'd appropriately to prevent further #ifdef's elsewhere. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6646/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for FTLBsLeonid Yegoshin2014-01-221-0/+3
| | | | | | | | | | | | | | The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
* MIPS: Provide nice way to access boot CPU's data.Ralf Baechle2013-09-171-0/+1
| | | | | | | | boot_cpu_data is used the same as current_cpu_data but returns the CPU data for CPU 0. This means it doesn't have to use smp_processor_id() thus no need to disable preemption. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-9/+9
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for presence of KScratch registers.David Daney2011-01-181-0/+1
| | | | | | | | | Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck2010-02-021-0/+3
| | | | | | | | | | | | | | Linux kernel 2.6.32 and later allocate address space from the top of the kernel virtual memory address space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/935/ Reviewed-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Outline udelay and fix a few issues.Ralf Baechle2009-06-081-2/+2
| | | | | | | | | | | | | | | Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.David Daney2008-10-111-0/+6
| | | | | | | | | | | This is the main support code for the patch. Here we just add the code, the following patches hook it up. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/watch.h create mode 100644 arch/mips/kernel/watch.c
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+84
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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