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path: root/arch/mips/include/asm/cpu-features.h
Commit message (Expand)AuthorAgeFilesLines
* MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen2013-05-081-0/+3
* Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle2013-02-211-0/+7
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| * MIPS: Probe for and report hardware virtualization support.David Daney2013-02-191-0/+4
| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-171-0/+3
* | MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill2013-02-151-0/+13
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-9/+9
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* MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill2012-10-111-0/+4
* MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper2012-10-111-0/+4
* MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-131-3/+0
* MIPS: Add base architecture support for RI and XI.Steven J. Hill2012-09-131-0/+3
* MIPS: Update comment for cpu_has_clo_clzRalf Baechle2010-08-051-1/+2
* MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-271-0/+3
* MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck2010-02-021-0/+7
* MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.David Daney2009-09-171-0/+3
* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-171-0/+4
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-171-0/+4
* MIPS: Enable CLO / CLZ instructions via separate CPU propertyRalf Baechle2009-05-141-0/+9
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-111-0/+3
* MIPS: New feature test macro cpu_has_mips_rRalf Baechle2008-10-301-0/+2
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+219
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