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* metag: Device treeJames Hogan2013-03-021-0/+23
| | | | | | | Add device tree files to arch/metag. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
* metag: TCM supportJames Hogan2013-03-023-0/+85
| | | | | | Add some TCM support Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Highmem supportJames Hogan2013-03-022-0/+161
| | | | Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Huge TLBJames Hogan2013-03-021-0/+86
| | | | | | Add huge TLB support to the metag architecture. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Memory handlingJames Hogan2013-03-022-0/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meta has instructions for accessing: - bytes - GETB (1 byte) - words - GETW (2 bytes) - doublewords - GETD (4 bytes) - longwords - GETL (8 bytes) All accesses must be aligned. Unaligned accesses can be detected and made to fault on Meta2, however it isn't possible to fix up unaligned writes so we don't bother fixing up reads either. This patch adds metag memory handling code including: - I/O memory (io.h, ioremap.c): Actually any virtual memory can be accessed with these helpers. A part of the non-MMUable address space is used for memory mapped I/O. The ioremap() function is implemented one to one for non-MMUable addresses. - User memory (uaccess.h, usercopy.c): User memory is directly accessible from privileged code. - Kernel memory (maccess.c): probe_kernel_write() needs to be overwridden to use the I/O functions when doing a simple aligned write to non-writecombined memory, otherwise the write may be split by the generic version. Note that due to the fact that a portion of the virtual address space is non-MMUable, and therefore always maps directly to the physical address space, metag specific I/O functions are made available (metag_in32, metag_out32 etc). These cast the address argument to a pointer so that they can be used with raw physical addresses. These accessors are only to be used for accessing fixed core Meta architecture registers in the non-MMU region, and not for any SoC/peripheral registers. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Memory managementJames Hogan2013-03-025-0/+767
| | | | | | | | | | | | | | | | | | | | | | | | Add memory management files for metag. Meta's 32bit virtual address space is split into two halves: - local (0x08000000-0x7fffffff): traditionally local to a hardware thread and incoherent between hardware threads. Each hardware thread has it's own local MMU table. On Meta2 the local space can be globally coherent (GCOn) if the cache partitions coincide. - global (0x88000000-0xffff0000): coherent and traditionally global between hardware threads. On Meta2, each hardware thread has it's own global MMU table. The low 128MiB of each half is non-MMUable and maps directly to the physical address space: - 0x00010000-0x07ffffff: contains Meta core registers and maps SoC bus - 0x80000000-0x87ffffff: contains low latency global core memories Linux usually further splits the local virtual address space like this: - 0x08000000-0x3fffffff: user mappings - 0x40000000-0x7fffffff: kernel mappings Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Cache/TLB handlingJames Hogan2013-03-025-0/+644
| | | | | | | | | | | | | | | | | Add cache and TLB handling code for metag, including the required callbacks used by MM switches and DMA operations. Caches can be partitioned between the hardware threads and the global space, however this is usually configured by the bootloader so Linux doesn't make any changes to this configuration. TLBs aren't configurable, so only need consideration to flush them. On Meta1 the L1 cache was VIVT which required a full flush on MM switch. Meta2 has a VIPT L1 cache so it doesn't require the full flush on MM switch. Meta2 can also have a writeback L2 with hardware prefetch which requires some special handling. Support is optional, and the L2 can be detected and initialised by Linux. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: TBX headerJames Hogan2013-03-021-0/+1425
| | | | | | | Add the main header for the Thread Binary Interface (TBI) library which provides useful low level operations and trap/context management. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: BootJames Hogan2013-03-022-0/+90
| | | | | | | | | | | | | | | | Add boot code for metag. Due to the multi-threaded nature of Meta it is not uncommon for an RTOS or bare metal application to be started on other hardware threads by the bootloader. Since there is a single MMU switch which affects all threads, the MMU is traditionally configured by the bootloader prior to starting Linux. The bootloader passes a structure to Linux which among other things contains information about memory regions which have been mapped. Linux then assumes control of the local heap memory region. A kernel arguments string pointer or a flattened device tree pointer can be provided in the third argument. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Header for core memory mapped registersJames Hogan2013-03-021-0/+1106
| | | | | | | Add the header <asm/metag_mem.h> describing addresses, fields, and bits of various core memory mapped registers in the low non-MMU region. Signed-off-by: James Hogan <james.hogan@imgtec.com>
* metag: Headers for core arch constantsJames Hogan2013-03-022-0/+1261
Add a couple of header files containing core architecture constants. The first (<asm/metag_isa.h>) contains some constants relating to the instruction set, such as values to give to the CACHEW and CACHER instructions. The second (<asm/metag_regs.h>) contains constants for the core register units directly accessible to various instructions, and for the registers, fields, and bits in those units. The main units described are the control unit (CT.*), the trigger unit (TR.*), and the run-time trace unit (TT.*). Signed-off-by: James Hogan <james.hogan@imgtec.com>
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