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* m68knommu: create optimal separate instruction and data cache for ColdFireGreg Ungerer2011-01-051-11/+20
| | | | | | | | | | | | | Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: support version 2 ColdFire split cacheGreg Ungerer2011-01-051-14/+16
| | | | | | | | | | The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: clean up ColdFire cache control codeGreg Ungerer2011-01-051-0/+27
| | | | | | | | | | | | | | | | | | The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: create bit definitions for the version 2 ColdFire cache controllerGreg Ungerer2011-01-051-0/+56
The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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