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* [IA64] Update Altix nofault codeRuss Anderson2008-01-031-3/+7
| | | | | | | | | | | Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Force error to surface in nofault codeRuss Anderson2007-06-261-1/+2
| | | | | | | | | | Montecito behaves slightly differently than previous processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. Adding an additional or and stop bits ensures the MCA surfaces in the nofault code. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] SGI Altix cross partition functionality (2ndDean Nelson2005-05-031-0/+31
This patch contains the shim module (XP) which interfaces between the communication module (XPC) and the functional support modules (like XPNET). Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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