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* [PATCH] Change maxaligned_in_smp alignemnt macros to internodealigned_in_smp ↵Ravikiran G Thirumalai2006-01-082-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | macros ____cacheline_maxaligned_in_smp is currently used to align critical structures and avoid false sharing. It uses per-arch L1_CACHE_SHIFT_MAX and people find L1_CACHE_SHIFT_MAX useless. However, we have been using ____cacheline_maxaligned_in_smp to align structures on the internode cacheline size. As per Andi's suggestion, following patch kills ____cacheline_maxaligned_in_smp and introduces INTERNODE_CACHE_SHIFT, which defaults to L1_CACHE_SHIFT for all arches. Arches needing L3/Internode cacheline alignment can define INTERNODE_CACHE_SHIFT in the arch asm/cache.h. Patch replaces ____cacheline_maxaligned_in_smp with ____cacheline_internodealigned_in_smp With this patch, L1_CACHE_SHIFT_MAX can be killed Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org> Signed-off-by: Shai Fultheim <shai@scalex86.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Swap Migration V5: sys_migrate_pages interfaceChristoph Lameter2006-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sys_migrate_pages implementation using swap based page migration This is the original API proposed by Ray Bryant in his posts during the first half of 2005 on linux-mm@kvack.org and linux-kernel@vger.kernel.org. The intent of sys_migrate is to migrate memory of a process. A process may have migrated to another node. Memory was allocated optimally for the prior context. sys_migrate_pages allows to shift the memory to the new node. sys_migrate_pages is also useful if the processes available memory nodes have changed through cpuset operations to manually move the processes memory. Paul Jackson is working on an automated mechanism that will allow an automatic migration if the cpuset of a process is changed. However, a user may decide to manually control the migration. This implementation is put into the policy layer since it uses concepts and functions that are also needed for mbind and friends. The patch also provides a do_migrate_pages function that may be useful for cpusets to automatically move memory. sys_migrate_pages does not modify policies in contrast to Ray's implementation. The current code here is based on the swap based page migration capability and thus is not able to preserve the physical layout relative to it containing nodeset (which may be a cpuset). When direct page migration becomes available then the implementation needs to be changed to do a isomorphic move of pages between different nodesets. The current implementation simply evicts all pages in source nodeset that are not in the target nodeset. Patch supports ia64, i386 and x86_64. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* x86: remove bogus 'pci=usepirqmask' suggestion when no irq is definedLinus Torvalds2006-01-061-1/+1
| | | | | | | | | | This was harmless, but for the case of a device that had no irq pre-defined we would incorrectly suggest that "usepirqmask" might make a difference. It never would, and the message was just confusing people. Reported in the dmesg of Etienne Lorrain. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: Handle HP laptop rebooting properly.Ben Collins2006-01-061-3/+3
| | | | | | Signed-off-by: Ben Collins <bcollins@ubuntu.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: ioapic virtual wire mode fixVivek Goyal2006-01-061-2/+2
| | | | | | | | | | | | | | | | | | | | | o Currently, during kexec reboot, IOAPIC is re-programmed back to virtual wire mode if there was an i8259 connected to it. This enables getting timer interrupts in second kernel in legacy mode. o After putting into virtual wire mode, IOAPIC delivers the i8259 interrupts to CPU0. This works well for kexec but not for kdump as we might crash on a different CPU and second kernel will not see timer interrupts. o This patch modifies the redirection table entry to deliver the timer interrupts to the cpu we are rebooting (instead of hardcoding to zero). This ensures that second kernel receives timer interrupts even on a non-boot cpu. Signed-off-by: Vivek Goyal <vgoyal@in.ibm.com> Cc: Andi Kleen <ak@muc.de> Cc: "Seth, Rohit" <rohit.seth@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] fix cpu frequency detection in ↵Larry Finger2006-01-061-0/+2
| | | | | | | | | | | | | | | | | arch/i386/kernel/timers/timer_tsc.c::recalibrate_cpu_khz() When we re-calibrate the frequency, it is likely that an interrupt (as for example the main system clock) will be triggered by the system. Therefore the calibration may not be accurate. This will also provide a fix to bug #5266. Many thanks to Larry Finger for helping resolving this issue. Signed-off-by: Bruno Ducrot <ducrot@poupinou.org> Cc: john stultz <johnstul@us.ibm.com> Cc: Dave Jones <davej@codemonkey.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] APM Screen Blanking fixJordan Crouse2006-01-061-13/+14
| | | | | | | | | | | | | | | | | - Fix screen blanking on BIOSes that return APM_NOT_ENGAGED when APM enabled screen blanking is not turned on. The original code only tried to set the state on device 0x100, and then 0x1FF, and I added 0x101 to the mix too. - Clean up logic in apm_console_blank(). - Prevent the error message from printing out twice. Cc: Jordan Crouse <jordan.crouse@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Base support for AMD Geode GX/LX processorsJordan Crouse2006-01-063-6/+42
| | | | | | | | | Provide basic support for the AMD Geode GX and LX processors. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] arch/i386/kernel/cpuid.c: unused variableDaniel Marjamaki2006-01-061-2/+1
| | | | | | | | | Removed the unused variable "rv". Signed-off-by: Daniel Marjamaki <daniel.marjamaki@comhem.se> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] arch/i386/kernel/msr.c: removed unused variableDaniel Marjamaki2006-01-061-2/+1
| | | | | | | | | Removed the unused variable "rv". Signed-off-by: Daniel Marjamaki <daniel.marjamaki@comhem.se> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: missing printk newline in apic boot option parserDave Jones2006-01-061-1/+1
| | | | | | | | Missing newline in printk. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: change_page_attr() fixDave Jones2006-01-061-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'make rodata read-only' patch in -mm exposes a latent bug in the 32-bit change_page_attr() function, which causes certain CPUs (Those with NX basically) to reboot instantly after pages are marked read-only. The same bug got fixed a while back on x86-64, but never got propagated to i386. Stuart Hayes from Dell also picked up on this last June, but it never got fixed, as the only thing affected by it aparently was the nvidia driver. Blatantly stealing description from his post.. "It doesn't appear to be fixed (in the i386 arch). The change_page_attr()/split_large_page() code will still still set all the 4K PTEs to PAGE_KERNEL (setting the _PAGE_NX bit) when a large page needs to be split. This wouldn't be a problem for the bulk of the kernel memory, but there are pages in the lower 4MB of memory that's free, and are part of large executable pages that also contain kernel code. If change_page_attr() is called on these, it will set the _PAGE_NX bit on the whole 2MB region that was covered by the large page, causing a large chunk of kernel code to be non-executable." Signed-off-by: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Dave Jones <davej@redhat.com> Cc: <Stuart_Hayes@Dell.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] make bigsmp the default mode if CONFIG_HOTPLUG_CPUAshok Raj2006-01-061-8/+18
| | | | | | | | | | If we are using hotplug enabled kernel, then make bigsmp the default mode. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386 sparsemem for single node systemsAndy Whitcroft2006-01-062-2/+14
| | | | | | | | | | | | | | Allow SPARSEMEM to be enabled on non-numa x86 systems. This is made dependant on EXPERIMENTAL also being set. When an in-tree user (such as simulated numa) exists it should be made dependant on that. The plan is to have no options and no selector as normal when !EXPERIMENTAL. When EXPERIMENTAL we enable the FLATMEM and SPARSEMEM options for X86_PC whilst maintaining DISCONTIGMEM and SPARSEMEM for NUMA. Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86/x86_64: mark rodata section read-only: make some datastructures ↵Arjan van de Ven2006-01-062-1/+1
| | | | | | | | | | | | | | | | | const Mark some key kernel datastructures readonly. This patch was previously posted on Jun 28th but was back then not merged because nothing was enforcing rodata anyway.. well that changed now :) Patch by Christoph Lameter <christoph@lameter.com> and Dave Jones <davej@redhat.com> Signed-off-by: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86/x86_64: mark rodata section read only: x86 partsArjan van de Ven2006-01-062-0/+34
| | | | | | | | | | | x86 specific parts to make the .rodata section read only Signed-off-by: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Adrian Bunk <bunk@stusta.de> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Deprecate useless bugZachary Amsden2006-01-061-11/+1
| | | | | | | | | | | | Remove the "temporary debugging check" which has managed to live for quite some time, and is clearly unneeded. The mm can never be live at this point, so clearly checking the LDT in the mm->context is redundant as well. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Apm is on cpu zero onlyZachary Amsden2006-01-061-12/+11
| | | | | | | | | | | APM BIOS code has a protective wrapper that runs it only on CPU zero. Thus, no need to set APM BIOS segments in the GDT for other CPUs. Signed-off-by: Zachary Amsden <zach@vmware.com> Acked-by: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Stop deleting ntZachary Amsden2006-01-061-5/+0
| | | | | | | | | | | Stop deleting NT bit from EFLAGS. See arch/i386/kernel/head.S line 223, which does something even better. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Fixed pnp bios limitsZachary Amsden2006-01-061-4/+8
| | | | | | | | | | | | | | | | PnP BIOS data, code, and 32-bit entry segments all have fixed limits as well; set them in the GDT rather than adding more code. It would be nice to add these fixups to the boot GDT rather than setting the GDT for each CPU; perhaps I can wiggle this in later, but getting it in before the subsys init looks tricky. Also, make some progress on deprecating the ugly Q_SET_SEL macros. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Pnp byte granularityZachary Amsden2006-01-061-6/+6
| | | | | | | | | | | | | | | | | | | | | | | The one remaining caller of set_limit, the PnP BIOS code, calls into the PnP BIOS, passing kernel parameters in and out. These parameteres may be passed from arbitrary kernel virtual memory, so they deserve strict protection to stop a bad BIOS from smashing beyond the object size. Unfortunately, the use of set_limit was badly botching this by setting the limit in terms of pages, when it really should have byte granularity. When doing this, I discovered my BIOS had the buggy code during the "get system device node" call: mov ax, es:[bx] Which is harmless, but has a trivial workaround. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Apm seg in gdtZachary Amsden2006-01-062-10/+5
| | | | | | | | | | | Since APM BIOS segment limits are now fixed, set them in head.S GDT and don't use the complicated _set_limit() macro expansion. Signed-off-by: Zachary Amsden <zach@vmware.com> Acked-by: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Always relax segmentsZachary Amsden2006-01-061-38/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | APM BIOSes have many bugs regarding proper representation of the appropriate segment limits for calling the BIOS. By default, APM_RELAX_SEGMENTS is always turned on to support running the APM BIOS on these buggy machines. Keeping 64k limits poses very little danger to the kernel, because the pages where the APM BIOS is located will always be in low physical memory BIOS areas, which should already be marked reserved, and only buggy BIOSes would possibly overstep the segment bounds with writes to data anyway. Since forcing stricter limits breaks many machines and is not default behavior, it seems reasonable to deprecate the older code which may cause APM BIOS to fault. If you really have a badly enough broken APM BIOS that you have to turn off APM_RELAX_SEGMENTS, seems like the best recourse here would be to disable the APM BIOS and / or not compile it into your kernel to begin with, and / or add your system to the known bad list. The reason I want to deprecate this code is there is underlying brokenness with the set_limit macros, and getting rid of many of the call sites rather than rewriting them seems to be the simplest and most correct course of action. Signed-off-by: Zachary Amsden <zach@vmware.com> Acked-by: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: Cr4 is valid on some 486sZachary Amsden2006-01-061-3/+1
| | | | | | | | | | | | | | So some 486 processors do have CR4 register. Allow them to present it in register dumps by using the old fault technique rather than testing processor family. Thanks to Maciej for noticing this. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: fix bound check IDT gateJan Beulich2006-01-061-2/+2
| | | | | | | | | | Other than apparently commonly assumed, the bound instruction does not require the corresponding IDT entry to have DPL 3. Acked-by: "Seth, Rohit" <rohit.seth@intel.com> Acked-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: move SIMD initializationJan Beulich2006-01-061-0/+22
| | | | | | | | Move some code unrelated to any dealing with hardware bugs from i386's bugs.h to a more logical place. Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: don't blindly enable interrupts in die()Jan Beulich2006-01-061-2/+5
| | | | | | | | | | | | Rather than blindly re-enabling interrupts in die(), save their state upon entry and then restore that state. If the kernel is in really bad condition and faults with interrupts disabled, re-enabling them in die() may cause even more trouble, implying more chances of data corruption. Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86: GDT alignment fixZachary Amsden2006-01-065-5/+11
| | | | | | | | | | | | | | | | Make GDT page aligned and page padded to support running inside of a hypervisor. This prevents false sharing of the GDT page with other hot data, which is not allowed in Xen, and causes performance problems in VMware. Rather than go back to the old method of statically allocating the GDT (which wastes unneded space for non-present CPUs), the GDT for APs is allocated dynamically. Signed-off-by: Zachary Amsden <zach@vmware.com> Cc: "Seth, Rohit" <rohit.seth@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: PTRACE_POKEUSR: allow changing RF bit in EFLAGS register.Chuck Ebbert2006-01-051-3/+6
| | | | | | | | | | | | | | | | | Setting RF (resume flag) allows a debugger to resume execution after a code breakpoint without tripping the breakpoint again. It is reset by the CPU after execution of one instruction. Requested by Stephane Eranian: "I am trying to the user HW debug registers on i386 and I am running into a problem with ptrace() not allowing access to EFLAGS_RF for POKEUSER (see FLAG_MASK). [ ... ] It avoids the need to remove the breakpoint, single step, and reinstall. The equivalent functionality exists on IA-64 and is allowed by ptrace()" Cc: Stephane Eranian <eranian@hpl.hp.com> Signed-off-by: Chuck Ebbert <76306.1226@compuserve.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386: "invalid operand" -> "invalid opcode"Chuck Ebbert2006-01-041-1/+1
| | | | | | | According to the manual, INT 6 is "invalid opcode", not "invalid operand". Signed-off-by: Chuck Ebbert <76306.1226@compuserve.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreqLinus Torvalds2006-01-048-44/+105
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| * [CPUFREQ] CPU frequency display in /proc/cpuinfoVenkatesh Pallipadi2005-12-061-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What is the value shown in "cpu MHz" of /proc/cpuinfo when CPUs are capable of changing frequency? Today the answer is: It depends. On i386: SMP kernel - It is always the boot frequency UP kernel - Scales with the frequency change and shows that was last set. On x86_64: There is one single variable cpu_khz that gets written by all the CPUs. So, the frequency set by last CPU will be seen on /proc/cpuinfo of all the CPUs in the system. What you see also depends on whether you have constant_tsc capable CPU or not. On ia64: It is always boot time frequency of a particular CPU that gets displayed. The patch below changes this to: Show the last known frequency of the particular CPU, when cpufreq is present. If cpu doesnot support changing of frequency through cpufreq, then boot frequency will be shown. The patch affects i386, x86_64 and ia64 architectures. Signed-off-by: Venkatesh Pallipadi<venkatesh.pallipadi@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] Move PMBASE reading away and do it only once at initialization timeMattia Dongili2005-12-061-13/+30
| | | | | | | | | | | | | | | | | | | | This patch moves away PMBASE reading and only performs it at cpufreq_register_driver time by exiting with -ENODEV if unable to read the value. Signed-off-by: Mattia Dongili <malattia@linux.it> Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] Measure transition latency at driver initializationMattia Dongili2005-12-064-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The attached patch introduces runtime latency measurement for ICH[234] based chipsets instead of using CPUFREQ_ETERNAL. It includes some sanity checks in case the measured value is out of range and assigns a safe value of 500uSec that should still be enough on problematics chipsets (current testing report values ~200uSec). The measurement is currently done in speedstep_get_freqs in order to avoid further unnecessary transitions and in the hope it'll come handy for SMI also. Signed-off-by: Mattia Dongili <malattia@linux.it> Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Dave Jones <davej@redhat.com> speedstep-ich.c | 4 ++-- speedstep-lib.c | 32 +++++++++++++++++++++++++++++++- speedstep-lib.h | 1 + speedstep-smi.c | 1 + 4 files changed, 35 insertions(+), 3 deletions(-)
| * Merge ../linus/Dave Jones2005-12-063-2/+17
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| * | [CPUFREQ] Change loglevels on powernow-k8 bios error printk's.Dave Jones2005-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | If a user has booted with 'quiet', some important messages don't get displayed which really should. We've seen at least one case where powernow-k8 stopped working, and the user needed a BIOS update that they didn't know about. Signed-off-by: Dave Jones <davej@redhat.com>
| * | [PATCH] cpufreq-nforce2.c fix u32<0 testGabriel A. Devenyi2005-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to LinuxICC (http://linuxicc.sf.net), a comparison of a u32 less than 0 was found, this patch changes the variable to a signed int so that comparison is meaningful. Signed-off-by: Gabriel A. Devenyi <ace@staticwave.ca> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] Fix indentation in powernow-k8Dave Jones2005-11-301-4/+4
| | | | | | | | | | | | Signed-off-by: Dave Jones <davej@redhat.com>
| * | Merge ../linusDave Jones2005-11-294-12/+8
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| * | | [PATCH] Support 100 MHz frequency transitionsLangsdorf, Mark2005-11-292-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Future versions of the Opteron processor may support frequency transitions of 100 MHz, instead of the=20 current 200 MHz. This patch enables the powernow-k8 driver to transition to an odd FID code, indicating a multiple of 100 MHz frequency. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * | | [CPUFREQ] Improve Error reporting in powernow-k8Jacob Shin2005-11-211-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up some error messages in the powernow-k8 driver and makes them more understandable. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>
* | | | [PATCH] x86: teach dump_task_regs() about the -8 offset.Stas Sergeev2005-12-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This should fix multi-threaded core-files Signed-off-by: stsp@aknet.ru Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] Fix build with CONFIG_PCI_MMCONFIGAndi Kleen2005-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now needs to include the type 1 functions ("direct") too. Reported by Pavel Roskin <proski@gnu.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] PCI: Fix dumb bug in mmconfig fixAndi Kleen2005-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use correct address when referencing mmconfig aperture while checking for broken MCFG. This was a typo when porting the code from 64bit to 32bit. It caused oopses at boot on some ThinkPads. Should definitely go into 2.6.15. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386,amd64: ioremap.c __iomem annotationsAl Viro2005-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386,amd64: mmconfig __iomem annotationsAl Viro2005-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386/x86-64 Correct for broken MCFG tables on K8 systemsAndi Kleen2005-12-121-3/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They report all busses as MMCONFIG capable, but it never works for the internal devices in the CPU's builtin northbridge. It just probes all func 0 devices on bus 0 (the internal northbridge is currently always on bus 0) and if they are not accessible using MCFG they are put into a special fallback bitmap. On systems where it isn't we assume the BIOS vendor supplied correct MCFG. Requires the earlier patch for mmconfig type1 fallback Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386/x86-64 Fall back to type 1 access when no entry foundAndi Kleen2005-12-123-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there is no entry for a bus in MCFG fall back to type1. This is especially important on K8 systems where always some devices can't be accessed using mmconfig (in particular the builtin northbridge doesn't support it for its own devices) Cc: <gregkh@suse.de> Cc: <jgarzik@pobox.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386/x86-64: Don't call change_page_attr with a spinlock heldAndi Kleen2005-12-121-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's illegal because it can sleep. Use a two step lookup scheme instead. First look up the vm_struct, then change the direct mapping, then finally unmap it. That's ok because nobody can change the particular virtual address range as long as the vm_struct is still in the global list. Also added some LinuxDoc documentation to iounmap. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] i386/x86-64 disable LAPIC completely for offline CPUShaohua Li2005-12-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabling LAPIC timer isn't sufficient. In some situations, such as we enabled NMI watchdog, there is still unexpected interrupt (such as NMI) invoked in offline CPU. This also avoids offline CPU receives spurious interrupt and anything similar. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Acked-by: "Seth, Rohit" <rohit.seth@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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