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In some cases it is desired to move a channel to a specific event queue.
Such a use case is audio, where it is preferred that it is served with
highest priority compared to other DMA clients.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Use the lowest priority queue as default for clients.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"This week's arm-soc fixes:
- Another set of OMAP fixes
* Clock fixes
* Restart handling
* PHY regulators
* SATA hwmod data for DRA7
+ Some trivial fixes and removal of a bit of dead code
- Exynos fixes
* A bunch of clock fixes
* Some SMP fixes
* Exynos multi-core timer: register as clocksource and fix ftrace.
+ a few other minor fixes
There's also a couple more patches, and at91 fix for USB caused by
common clock conversion, and more MAINTAINERS entries for shmobile.
We're definitely switching to only regression fixes from here on out,
we've been a little less strict than usual up until now"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
ARM: at91: at91sam9x5: add clocks for usb device
ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
ARM: dts: Add clock property for mfc_pd in exynos5420
clk: exynos5420: Add IDs for clocks used in PD mfc
ARM: EXYNOS: Add support for clock handling in power domain
ARM: OMAP2+: Remove non working OMAP HDMI audio initialization
ARM: imx: fix shared gate clock
ARM: dts: Update the parent for Audss clocks in Exynos5420
ARM: EXYNOS: Update secondary boot addr for secure mode
ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA.
ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio
ARM: dts: am335x-evm: Enable the McASP FIFO for audio
ARM: OMAP2+: Make GPMC skip disabled devices
ARM: OMAP2+: create dsp device only on OMAP3 SoCs
ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on
ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: DRA7: hwmod: Fixup SATA hwmod
ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver
...
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-3 for 3.16" from Kukjin Kim:
Samsung fixes-3 for v3.16
- update the parent for Auudss clock because kernel will be hang
during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
on/off, its regarding clock source will be reset and it causes
a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
system failure will be happened on other exynos SoCs.
* tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
ARM: dts: Add clock property for mfc_pd in exynos5420
clk: exynos5420: Add IDs for clocks used in PD mfc
ARM: EXYNOS: Add support for clock handling in power domain
ARM: dts: Update the parent for Audss clocks in Exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
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Currently, the exynos cpuidle driver works correctly only on exynos4210
and 5250. Trying to use it with just one CPU online on any other exynos
SoCs will lead to system failure, due to unsupported AFTR mode on other
SoCs. This patch fixes the problem by registering the driver only on
supported SoCs and letting others simply use default WFI mode until
support for them is added.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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While powering on/off a local powerdomain in exynos5 chipsets, the
input clocks to each device gets modified. This behaviour is based
on the SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on
a domain everytime.
This patch adds the framework for getting the required mux and parent
clocks through a power domain device node. With this patch, while
powering off a domain, parent is set to oscclk and while powering back
on, its re-set to the correct parent which is as per the recommended
pd on/off sequence.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Add clocks for usb device, or else switch to CCF, the gadget
won't work.
Reported-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.16-rc4" from Tony Lindgren:
Fixes for omaps for the -rc series. It's mostly fixes for clock rates,
restart handling and phy regulators and SATA interconnect data.
Also few build fixes related to the DSP driver in staging, and trivial
stuff like removal of broken and soon to be unused platform data init
for HDMI audio that would be good to get into the -rc series if not
too late.
* tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Remove non working OMAP HDMI audio initialization
ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA.
ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio
ARM: dts: am335x-evm: Enable the McASP FIFO for audio
ARM: OMAP2+: Make GPMC skip disabled devices
ARM: OMAP2+: create dsp device only on OMAP3 SoCs
ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on
ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: DRA7: hwmod: Fixup SATA hwmod
ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver
ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Signed-off-by: Olof Johansson <olof@lixom.net>
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This code is not working currently and it can be removed. There is a
conflict in sharing resources with the actual HDMI driver and with
the ASoC HDMI audio DAI driver.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.16/fixes
Some miscellaneous fixes for OMAP clock code, DRA7xx device data, and
PRCM code (when DSPBridge is used) for v3.16-rc.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/prcm-a-v3.16-rc/20140706174258/
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The divider value provided to the _dpll_test_fint can reach value of
256 with J type DPLLs (USB etc.), which causes an overflow with the u8
datatype. Fix this by changing the parameter to be an int instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: changed type of 'n' to unsigned int]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Get rid of optional clock as that is now managed by the
AHCI platform driver.
Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The commit 7be914f {ARM: OMAP3: PRM/CM: Cleanup unused header} removed
some of the macros used by the TI DSP/Bridge driver. This fixes the
following build errors when trying to build DSP/Bridge driver (disabled
at present), otherwise results in the following build errors:
drivers/staging/tidspbridge/core/tiomap3430.c:531:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430.c:531:31: note: each undeclared identifier is reported only once for each function it appears in
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430.o] Error 1
make[3]: *** Waiting for unfinished jobs....
drivers/staging/tidspbridge/core/tiomap_io.c: In function 'sm_interrupt_dsp':
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:404:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap_io.c:414:12: error: 'OMAP3430_IVA2_DPLL_FREQSEL_SHIFT' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap_io.c:415:12: error: 'OMAP3430_EN_IVA2_DPLL_SHIFT' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap_io.o] Error 1
drivers/staging/tidspbridge/core/tiomap3430_pwr.c: In function 'dsp_clk_wakeup_event_ctrl':
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: error: 'OMAP3430_GRPSEL_GPT5_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: note: each undeclared identifier is reported only once for each function it appears in
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:455:19: error: 'OMAP3430_GRPSEL_GPT6_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:468:19: error: 'OMAP3430_GRPSEL_GPT7_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:481:19: error: 'OMAP3430_GRPSEL_GPT8_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:494:19: error: 'OMAP3430_GRPSEL_MCBSP1_MASK' undeclared (first use in this function)
drivers/staging/tidspbridge/core/tiomap3430_pwr.c:546:19: error: 'OMAP3430_GRPSEL_MCBSP5_MASK' undeclared (first use in this function)
make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430_pwr.o] Error 1
make[2]: *** [drivers/staging/tidspbridge] Error 2
Fixes: 7be914f (ARM: OMAP3: PRM/CM: Cleanup unused header)
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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https://github.com/t-kristo/linux-pm into fixes-rc4
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Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000
With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000
The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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As this board use external clock for RMII interface we should specify 'rmii'
phy mode and 'rmii-clock-ext' to make ethernet working.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently, child nodes of the gpmc node are iterated and probed
regardless of their 'status' property. This means adding 'status =
"disabled";' has no effect.
This patch changes the iteration to only probe nodes marked as
available.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The DSP platform device for TI DSP/Bridge is currently
created unconditionally whenever CONFIG_TIDSPBRIDGE is
enabled. This device should only be created on OMAP34xx/
OMAP36xx SoCs, and not for other OMAP3 derived SoCs or when
booting multi-arch images on other SoCs. So, add a check for
the SoC family both before creating the device and allocating
the carveout memory for the device.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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After clarification from the hardware team it was found that
this 1.8V PHY supply can't be switched OFF when SoC is Active.
Since the PHY IPs don't contain isolation logic built in the design to
allow the power rail to be switched off, there is a very high risk
of IP reliability and additional leakage paths which can result in
additional power consumption.
The only scenario where this rail can be switched off is part of Power on
reset sequencing, but it needs to be kept always-on during operation.
This patch is required for proper functionality of USB, SATA
and PCIe on DRA7-evm.
CC: Rajendra Nayak <rnayak@ti.com>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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omap44xx_restart is defined as a static void inline when DRA7/AM437X is
defined alone, which implies that the restart function is no longer
functional even though it is built in. So, fix the definition of the
same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Let's say clock A and B are two gate clocks that share the same register
bit in hardware. Therefore they are registered as shared gate clocks
with imx_clk_gate2_shared().
In a scenario that only clock A is enabled by clk_enable(A) while B is
not used, the shared gate will be unexpectedly disabled in hardware.
It happens because clk_enable(A) increments the share_count from 0 to 1,
while clock B is unused to clock core, and therefore the core function
will just disable B by calling clk->ops->disable() directly. The
consequence of that call is share_count is decremented to 0 and the gate
is disabled in hardware, even though clock A is still in use.
The patch fixes the issue by initializing the share_count per hardware
state and returns enable state per share_count from .is_enabled() hook,
in case it's a shared gate.
While at it, add a check in clk_gate2_disable() to ensure it's never
called with a zero share_count.
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support")
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-2 for v3.16" from Kukjin Kim:
- fix the check for SMP configuration with using CONFIG_SMP
not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Update secondary boot addr for secure mode
clocksource: exynos_mct: Register the timer for stable udelay
clocksource: exynos_mct: Fix ftrace
ARM: dts: fix pwm-cells in pwm node for exynos4
ARM: EXYNOS: Fix the check for non-smp configuration
Signed-off-by: Olof Johansson <olof@lixom.net>
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Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with Exynos4412 being the only
exception.
Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420).
While at it, fix the coding style (space around *).
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Tested-by: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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pwm-cells should be 3. Third cell is optional PWM flags. And This flag
supported by this binding is PWM_POLARITY_INVERTED.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Commit 1754c42e3db5("ARM: exynos: move sysram info to exynos.c") missed
out the CONFIG_ prefix causing exynos_sysram_init() to get called twice
for SMP configurations.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsug.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Pull ARM fixes from Russell King:
"Another round of fixes for ARM:
- a set of kprobes fixes from Jon Medhurst
- fix the revision checking for the L2 cache which wasn't noticed to
have been broken"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: l2c: fix revision checking
ARM: kprobes: Fix test code compilation errors for ARMv4 targets
ARM: kprobes: Disallow instructions with PC and register specified shift
ARM: kprobes: Prevent known test failures stopping other tests running
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into fixes
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Conditionally compile kprobes test cases for ARMv5 instructions to avoid
compilation errors with ARMv4 targets like:
/tmp/cc7Tx8ST.s:16740: Error: selected processor does not support ARM mode `clz r0,r0'
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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ARM data processing instructions which have a register specified shift
are defined as UNPREDICTABLE if PC is used for any register, not just
the shift value as the code was previous assuming. This issue manifests
on A15 devices as either test case failures or undefined instructions
aborts.
Reported-by: David Long <dave.long@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Due to a long-standing issue with Thumb symbol lookup [1] the jprobes
tests fail when built into a kernel compiled as Thumb mode. (They work
fine for ARM mode kernels or for Thumb when built as a loadable module.)
Rather than have this problem terminate testing prematurely lets instead
emit an error message and carry on with the main kprobes tests, delaying
the final failure report until the end.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/063026.html
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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The revision checking in l2c310_enable() was not correct; we were
masking the part number rather than the revision number. Fix this
to use the correct macro.
Fixes: 4374d64933b1 ("ARM: l2c: add automatic enable of early BRESP")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"This week's arm-soc fixes:
- A set of of OMAP patches that we had missed Tony's pull request of:
* Reset fix for am43xx
* Proper OPP table for omap5
* Fix for SoC detection of one of the DRA7 SoCs
* hwmod updates to get SATA and OCP to work on omap5 (drivers
merged in 3.16)
* ... plus a handful of smaller fixes
- sunxi needed to re-add machine specific restart code that was
removed in anticipation of a watchdog driver being merged for 3.16,
and it didn't make it in.
- Marvell fixes for PCIe on SMP and a big-endian fix.
- A trivial defconfig update to make my capri test board boot with
bcm_defconfig again.
... and a couple of MAINTAINERS updates, one to claim new Keystone
drivers that have been merged, and one to merge MXS and i.MX (both
Freescale platforms).
The largest diffs come from the hwmod code for omap5 and the re-add of
the restart code on sunxi. The hwmod stuff is quite late at this
point but it slipped through cracks repeatedly while coming up the
maintainer chain and only affects the one SoC so risk is low"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: Add few more Keystone drivers
MAINTAINERS: merge MXS entry into IMX one
ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs
ARM: mvebu: fix cpuidle implementation to work on big-endian systems
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
ARM: mvebu: move Armada 375 external abort logic as a quirk
ARM: bcm: Fix bcm and multi_v7 defconfigs
ARM: dts: dra7-evm: remove interrupt binding
ARM: OMAP2+: Fix parser-bug in platform muxing code
ARM: DTS: dra7/dra7xx-clocks: ATL related changes
ARM: OMAP2+: drop unused function
ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
ARM: dts: omap5: Update CPU OPP table as per final production Manual
ARM: DRA722: add detection of SoC information
ARM: dts: Enable twl4030 off-idle configuration for selected omaps
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
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mvebu fixes for v3.16 (round #2)
- mvebu
- Fix PCIe deadlock now that SMP is enabled
- Fix cpuidle for big-endian systems
* tag 'mvebu-fixes-3.16-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: fix cpuidle implementation to work on big-endian systems
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
ARM: mvebu: move Armada 375 external abort logic as a quirk
Signed-off-by: Olof Johansson <olof@lixom.net>
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On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.
While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.
Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.
Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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In preparation to a small re-organization of the initialization
sequence in board-v7.c, this commit moves the registration of the
custom external abort handler on Armada 375 later in the boot
sequence, and makes it more similar to the other quirks that we
already have. There is indeed no need to register this abort handler
particularly early, it simply needs to be registered before switching
to userspace.
In addition to this, this commit makes the registration of the custom
abort handler conditional on Armada 375 Z1, because Armada 375 A0 and
later iterations are not affected by the issue.
This commit was tested on both Armada 375 Z1 and Armada 375 A0
platforms.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This partly reverts commits 553600502b84 (ARM: sunxi: Remove reset code from
the platform) and 5e669ec583e2 (ARM: sunxi: Remove init_machine callback) for
the sun4i, sun5i and sun7i families.
This is needed because the watchdog counterpart of these commits was dropped,
and didn't make it into 3.16. In order to still be able to reboot the board, we
need to reintroduce that code. Of course, the long term view is still to get
rid of that code in mach-sunxi.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge OMAP fixes from Tony Lindgren:
Fixes for omaps for issues discovered during the merge window and
enabling of a few features that had to wait for the driver
dependencies to clear.
The fixes included are:
- Fix am43xx hard reset flags
- Fix SoC detection for DRA722
- Fix CPU OPP table for omap5
- Fix legacy mux parser bug if requested muxname is a prefix of
multiple mux entries
- Fix qspi interrupt binding that relies on the irq crossbar
that has not yet been enabled
- Add missing phy_sel for am43x-epos-evm
- Drop unused gic_init_irq() that is no longer needed
And the enabling of features that had driver dependencies are:
- Change dra7 to use Audio Tracking Logic clock instead of a fixed
clock now that the clock driver for it has been merged
- Enable off idle configuration for selected omaps as all the kernel
dependencies for device tree based booting are finally merged as
this is needed to get the automated PM tests working finally with
device tree based booting
- Add hwmod entry for ocp2scp3 for omap5 to get sata working as
all the driver dependencies are now in the kernel and this patch
fell through the cracks during the merge window
* tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7-evm: remove interrupt binding
ARM: OMAP2+: Fix parser-bug in platform muxing code
ARM: DTS: dra7/dra7xx-clocks: ATL related changes
ARM: OMAP2+: drop unused function
ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
ARM: dts: omap5: Update CPU OPP table as per final production Manual
ARM: DRA722: add detection of SoC information
ARM: dts: Enable twl4030 off-idle configuration for selected omaps
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
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The qspi node defines crossbar number as its interrupt number. But,
the crossbar dts patches are not yet there, this causes a warning during
boot. So interrupts = < > property should be removed from DT and added
later by crossbar series.
Reported-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Fix a parser-bug in the omap2 muxing code where muxtable-entries will be
wrongly selected if the requested muxname is a *prefix* of their
m0-entry and they have a matching mN-entry. Fix by additionally checking
that the length of the m0_entry is equal.
For example muxing of "dss_data2.dss_data2" on omap32xx will fail
because the prefix "dss_data2" will match the mux-entries "dss_data2" as
well as "dss_data20", with the suffix "dss_data2" matching m0 (for
dss_data2) and m4 (for dss_data20). Thus both are recognized as signal
path candidates:
Relevant muxentries from mux34xx.c:
_OMAP3_MUXENTRY(DSS_DATA20, 90,
"dss_data20", NULL, "mcspi3_somi", "dss_data2",
"gpio_90", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", NULL, NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
This will result in a failure to mux the pin at all:
_omap_mux_get_by_name: Multiple signal paths (2) for dss_data2.dss_data2
Patch should apply to linus' latest master down to rather old linux-2.6
trees.
Signed-off-by: David R. Piegdon <lkml@p23q.org>
Cc: stable@vger.kernel.org
[tony@atomide.com: updated description to include full description]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Modify the clock nodes for the ATL clocks to use the ATL clock driver to
handle them.
Add the ATL device node at the same time for DRA7.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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gic_init_irq() is no longer used as of:
commit b42b918194c4791510ac049e3d507169a7de8544
Author: Tony Lindgren <tony@atomide.com>
Date: Thu May 30 12:53:05 2013 -0700
ARM: OMAP2+: Remove board-omap4panda.c
Drop it.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
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AM437x EPOS evm use external clock for RMII interface.
Enable the same in DT.
Signed-off-by: George Cherian <george.cherian@ti.com>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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As per the Final production Data Manual for OMAP5432,
SWPS050F(APRIL 2014)
There are only two OPPs - 1GHz and 1.5GHz. the older OPP_LOW has been
completely descoped. The Nominal voltages are still correct though.
However, expectation for final production configuration is operation
with Adaptive Body Bias (ABB) and Adaptive Voltage Scaling Class 0
operation.
There are no IDcode or version change information encoded to
programmatically detect this and software is supposed to NOT use
OPP_LOW(500MHz) anymore for all devices (legacy and production
samples).
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add support for DRA72x device DIEID. Currently these devices are
reported as DRA75/74 family of processors.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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