| Commit message (Collapse) | Author | Age | Files | Lines |
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DMTIMER source selection on OMAP1 is broken. omap1_dm_timer_set_src()
tries to use __raw_{read,write}l() to read from and write to physical
addresses, but those functions take virtual addresses.
sparse caught this:
arch/arm/mach-omap1/timer.c:50:13: warning: incorrect type in argument 1 (different base types)
arch/arm/mach-omap1/timer.c:50:13: expected void const volatile [noderef] <asn:2>*<noident>
arch/arm/mach-omap1/timer.c:50:13: got unsigned int
arch/arm/mach-omap1/timer.c:52:9: warning: incorrect type in argument 1 (different base types)
arch/arm/mach-omap1/timer.c:52:9: expected void const volatile [noderef] <asn:2>*<noident>
arch/arm/mach-omap1/timer.c:52:9: got unsigned int
Fix by using omap_{read,writel}(), just like the other users of the
MOD_CONF_CTRL_1 register in the OMAP1 codebase. Of course, in the long term,
removing omap_{read,write}l() is the appropriate thing to do; but
this will take some work to do this cleanly.
Looks like this was caused by 97933d6 (ARM: OMAP1: dmtimer: conversion
to platform devices) that dangerously moved code and changed it in
the same patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Cc: stable@vger.kernel.org
[tony@atomide.com: updated comments to include the breaking commit]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The current serial UART code, while fidling with ocp idlemode bits,
forget about the smart idle wakeup bit even if it is supported by
UART IP block. This will lead to missing the module wakeup on OMAP's
where the smart idle wakeup is supported.
This was the root cause of the console sluggishness issue, I have been
observing on OMAP4 devices and also can be potential reason for some
other UART wakeup issues.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Govindraj.R <govindraj.raja@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Commit (7496ba3 ARM: OMAP2+: UART: Add default mux for all uarts)
wrongly added muxing of default pads for all uarts. This causes
breakage on multiple boards using uart pins for alternate functions.
For example, on zoom3 random oopses can be seen with nfsroot as
the smsc911x ethernet FIFO timings on GPMC bus are controlled
by gpmc_wait2 and gpmc_wait3 pins. This means we can't mux these
pads to uart4 functionality as commit 7496ba3 was doing.
Not all boards tend to use all uarts and most of unused uart pins
are muxed for other purpose. This commit breaks the modules which
where trying to use unused uart pins on their boards.
So remove the default pad muxing. Note that this is not a complete
fix, as we now rely on bootloader set muxing for the uart wake-up
events. Further patching is needed to enable wake-up events for
uarts that are already muxed to uart mode.
Cc: Felipe Balbi <balbi@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Acked-by: Russ Dill <russ.dill@gmail.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
[tony@atomide.com: updated comments to describe oops on zoom3]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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_omap3_sram_configure_core_dpll is called when SDRC is reprogrammed,
which is done regardless of CONFIG_PM setting, so we always need it's
setup code too. Without this, we hit a BUG() on OMAP3 when kernel is
built without CONFIG_PM:
Reprogramming SDRC clock to 332000000 Hz
------------[ cut here ]------------
kernel BUG at arch/arm/plat-omap/sram.c:342!
Internal error: Oops - BUG: 0 [#1] ARM
...
[<c001c694>] (omap3_configure_core_dpll+0x68/0x6c) from [<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x1)
[<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x138/0x1b0) from [<c001a478>] (omap2_clk_set_rate+0x14/0x2)
[<c001a478>] (omap2_clk_set_rate+0x14/0x20) from [<c001c9dc>] (clk_set_rate+0x54/0x74)
[<c001c9dc>] (clk_set_rate+0x54/0x74) from [<c022b9c8>] (omap_sdrc_init+0x70/0x90)
[<c022b9c8>] (omap_sdrc_init+0x70/0x90) from [<c022f178>] (omap3pandora_init+0x11c/0x164)
[<c022f178>] (omap3pandora_init+0x11c/0x164) from [<c022849c>] (customize_machine+0x20/0x28)
[<c022849c>] (customize_machine+0x20/0x28) from [<c0225810>] (do_one_initcall+0xa0/0x16c)
[<c0225810>] (do_one_initcall+0xa0/0x16c) from [<c02259e0>] (kernel_init+0x104/0x1ac)
[<c02259e0>] (kernel_init+0x104/0x1ac) from [<c0009cec>] (kernel_thread_exit+0x0/0x8)
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
A few OMAP hwmod fixes against v3.4-rc2. One of them is a reversion
of a previous v3.4-rc patch that caused some regressions, and upon
further review, appears not to be necessary. The other two are fairly
minor.
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interface
The clocks for all DSS slave interfaces were recently changed to "dss_ick" on
OMAP2 and OMAP3, this clock can be autoidled by PRCM. The VENC interface
previously had "dss_54m_fck" as it's clock which couldn't be autoidled, and
hence the OCPIF_SWSUP_IDLE flag was needed.
Remove the OCPIF_SWSUP_IDLE flag from VENC interfaces as it's clock is
now "dss_ick". This allows the PRCM hardware to autoidle the VENC
interface clocks when they are not active, rather than relying on the
software to do it, which can keep the interface clocks active
unnecessarily.
Signed-off-by: Archit Taneja <archit@ti.com>
[paul@pwsan.com: add a short description of the fix to the commit log]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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wait for reset status"
This reverts commit f9a2f9c3fa76eec55928e8e06f3094c8f01df7cb. This
commit caused a regression in the I2C hwmod reset on OMAP2/3/4,
logging messages similar to these during boot:
[ 0.200378] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
[ 0.222076] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
While the original patch was intended to fix some reset-related timing
issues, it's believed that these problems were actually fixed by
commit 2800852a079504f35f88e44faf5c9c96318c0cca ("ARM: OMAP2+: hwmod:
Restore sysc after a reset"):
http://marc.info/?l=linux-arm-kernel&m=133410322617245&w=2
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Due to HW limitation, some IPs should not be accessed just after a
softreset. Since the current hwmod sequence is accessing the sysconfig
register just after the reset, it might lead to OCP bus error in
that case.
Add a new field in the sysconfig structure to specify a delay in usecs
needed after doing a softreset.
In the case of the ISS and FDIF modules, the L3 OCP port will be
disconnected upon a SW reset. That issue was confirmed with HW simulation
and an errata should be available soon. The HW recommendation to avoid
that is to wait for 100 OCP clk cycles, before accessing the IP.
Considering the worse case (OPP50), the L3 bus will run at 100 MHz,
so a 1 usec delay is needed. Add an x2 margin to be safe.
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com>
[paul@pwsan.com: dropped FDIF change for now since the hwmod data is not
yet upstream; the FDIF change will need to be added later once the FDIF
data is merged]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Fix the following build breakage in v3.4-rc2 that happens
with CONFIG_OMAP_MUX=y:
arch/arm/mach-omap1/mux.c:89:1: error: 'FUNC_MUX_CTRL_9' undeclared here (not in a function)
arch/arm/mach-omap1/mux.c:89:1: error: 'PULL_DWN_CTRL_2' undeclared here (not in a function)
arch/arm/mach-omap1/mux.c:93:1: error: 'FUNC_MUX_CTRL_C' undeclared here (not in a function)
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: SoC fixes: from Olof Johansson:
"A bunch of fixes for regressions (and a few other problems) in
3.4-rc1:
- Fix for regression of mach/io.h cleanup on platforms with PCI or
PCMCIA (adding back the include file on those for now)
- AT91 fixes for usb and spi
- smsc911x ethernet fixes for i.MX
- smsc911x fixes for OMAP
- gpio fixes for Tegra
- A handful of build error and warning fixes for various platforms
- cpufreq kconfig dependencies, build and lowlevel debug fixes for
Samsung platforms
In other words, more or less the regular collection of -rc1/2 type
material. A few of them, in particular the smsc911x for OMAP series,
aren't technically regressions for 3.4, but they're valid fixes and
we're still relatively early in the rc cycle so it seems appropriate
to include them."
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
ARM: fix __io macro for PCMCIA
ARM: EXYNOS: Fix compiler warning in dma.c file
ARM: EXYNOS: fix ISO C90 warning
ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions
ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status
ARM: OMAP2+: hwmod: Restore sysc after a reset
ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules
ARM: OMAP3: clock data: fill in some missing clockdomains
ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL
ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()
gpio: tegra: Iterate over the correct number of banks
gpio: tegra: fix register address calculations for Tegra30
EXYNOS: fix dependency for EXYNOS_CPUFREQ
ARM: at91: dt: remove unit-address part for memory nodes
ARM: at91: fix check of valid GPIO for SPI and USB
USB: ehci-atmel: add needed of.h header file
ARM: at91/NAND DT bindings: add comments
ARM: at91/at91sam9x5.dtsi: fix NAND ale/cle in DT file
USB: ohci-at91: trivial return code name change
...
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
From Paul Walmsley:
OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the
early v3.4-rc series. Also contains an HSMMC integration refinement
of an earlier hardware bug workaround.
* tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending:
ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions
ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status
ARM: OMAP2+: hwmod: Restore sysc after a reset
ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules
ARM: OMAP3: clock data: fill in some missing clockdomains
ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL
ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()
ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases
ARM: OMAP: clock: fix race in disable all clocks
ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks
ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks
ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached
ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data
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'hsmmc_erratum_2_1_1_128_refine_3.4rc1', 'hwmod_data_fixes_a_3.4rc', 'hwmod_fixes_a2_3.4rc' and 'powerdomain_fixes_a_3.4rc' into omap-fixes-a2-for-3.4rc-branch
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pwrdm_state_switch()
Commit b1cbdb00d ("OMAP: clockdomain: Wait for powerdomain to be ON
when using clockdomain force wakeup") was assuming that
pwrdm_state_switch() does wait for the powerdomain transition which is
not the case. The missing wait for the powerdomain transition
violates the sequence which the hardware expects, which causes power
management failures on some devices.
Fix this API by adding the pwrdm_wait_transition().
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: added some more details in the commit log]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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In the SYSC_TYPE1_XXX_MASK configuration, SYSC_XXX_SHIFT macro
is used which is not defined anywhere in the kernel.
Until now the build was going through successfully, since it
is not being used anywhere in kernel.
This bug got introduced by the commit
358f0e630d5409ab3837b86db3595560eae773b6 ("OMAP3: hwmod: support
to specify the offset position of various SYSCONFIG register bits.")
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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omap_hwmod_softreset() does not seem to wait for reset status
after doing a softreset. Make it use _ocp_softreset() instead
which does this correctly.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Anand Gadiyar <gadiyar@ti.com>
Cc: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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After a softreset, make sure the sysc settings are correctly
restored.
Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shubhrajyoti D <shubhrajyoti@ti.com>
[paul@pwsan.com: combined post-reset SYSCONFIG reload code into the
_reset() function to avoid duplication and future mistakes]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available (ex: usb
host uhh module) in absence of this flag
omap_hwmod_enable/disable_wakeup avoids configuring pad mux wakeup
capability.
Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
try enabling/disabling wakeup from mux_pad pins.
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
[paul@pwsan.com: updated function kerneldoc documentation]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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CLKS signal for McBSP ports can be selected from internal (PRCM) or
external (ABE_CLKS pin) source. To be able to use existing code we
need to create clock aliases consistent among OMAP2/3/4.
Based on a patch from Péter Ujfalusi <peter.ujfalusi@ti.com>;
the patch description above is his.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Péter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
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If transceiver is attached to a MMC host of ES2.1 OMAP35xx, it seems
2.1.1.128 erratum doesn't apply and there is no data corruption,
probably because of different signal timing. The workaround for this
erratum disables multiblock reads, which causes dramatic loss of
performance (over 75% slower), so avoid it when transceiver is present.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
[paul@pwsan.com: edited commit message slightly]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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According to the 4430 ES2.0 TRM vX Table 3-744 "CM_EMU_CLKSTCTRL",
the emu_sys clockdomain data in mainline is incorrect.
The emu_sys clockdomain does not support the DISABLE_AUTO state, and
instead it supports the FORCE_WAKEUP state.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
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Several clocks are missing clockdomains. This can cause problems with
the hwmod and power management code. Fill these in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Matt Porter <mporter@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
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All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.
Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.
Cc: Nishanth Menon <nm@ti.com>
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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According to OMAP4 TRM Table 3-1183, CM_CLKSEL_DPLL_USB register defines
following fields for multiplication and division factors:
DPLL_MULT (bits 19:8) DPLL multiplier factor (2 to 4095)
DPLL_DIV (bits 7:0) DPLL divider factor (0 to 255)
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Rename EMAC clocks to match driver expectations: both davinci_emac and
davinci_mdio drivers call clk_get(dev, NULL) so we have to provide
("davinci_emac", NULL) and ("davinci_mdio.0", NULL) clocks instead of
("davinci_emac", "emac_clk") and ("davinci_emac", "phy_clk") resp.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
Since clk_disable_unused is called as lateinitcall, there can
be more than a few workqueues executing off secondary CPU(s).
The current code does the following:
a) checks if clk is unused
b) holds lock
c) disables clk
d) unlocks
Between (a) and (b) being executed on CPU0, It is possible to
have a driver executing on CPU1 which could do a get_sync->clk_get
(and increase the use_count) of the clock which was just about
to be disabled by clk_disable_unused.
We ensure instead that the entire list traversal is protected by
the lock allowing for parent child clock traversal which could be
potentially be done by runtime operations to be safe as well.
Reported-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Commit 2a9f5a4d455 "OMAP3 clock: remove unnecessary duplicate of dpll4_m2_ck,
added for 36xx" consolidated dpll4 clock structures between 34xx and 36xx,
but left 34xx CLKSEL masks for most dpll4 related clocks, which causes
clock code to not behave correctly when booting on DM3730 with higher
(36xx only) divisors set:
[ 0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:375 omap2_init_clksel_parent+0x104/0x114()
[ 0.000000] clock: dpll4_m3_ck: init parent: could not find regval 0
[ 0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:194 omap2_clksel_recalc+0xd4/0xe4()
[ 0.000000] clock: Could not find fieldval 0 for clock dpll4_m3_ck parent dpll4_ck
Fix this by switching to 36xx masks, as valid divisors will be limited
by clksel_rate lists.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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With commit c334bc1 (ARM: make mach/io.h include optional), PCMCIA was
broken. PCMCIA depends on __io() returning a valid i/o address, and most
ARM platforms require IO_SPACE_LIMIT be set to 0xffffffff for PCMCIA. This
needs a better fix with a fixed i/o address mapping, but for now we just
restore things to the previous behavior.
This fixes at91, omap1, pxa and sa11xx. pxa needs io.h if PCI is enabled,
but PCMCIA is not. sa11xx already has IO_SPACE_LIMIT set to 0xffffffff,
so it doesn't need an io.h.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Joachim Eastwood <joachim.eastwood@jotron.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Tested-by: Paul Parsons <lost.distance@yahoo.com> (pxa270)
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
* 'v3.4-samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Fix compiler warning in dma.c file
ARM: EXYNOS: fix ISO C90 warning
ARM: EXYNOS: use chip_id reg in uncompress to select uart base phys
ARM: EXYNOS: fix CONFIG_DEBUG_LL
ARM: S3C24XX: fix missing common.h in mach-s3c24xx/
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Fixes the following warning:
warning: 'dma_dmamask' defined but not used [-Wunused-variable]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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ISO C90 forbids mixed declarations and code.
Fix it.
Signed-off-by: Il Han <corone.il.han@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Signed-off-by: Dima Zavin <dima@android.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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addruart cannot read from the physical address of the chipid
register, that will fail as soon as the mmu is turned on.
Fixing it to read from the physical or virtual address depending
on the mmu state also does not work, because there is a period
between head.S and exynos_map_io where the mmu is on, the uart
is mapped and used, but the chipid mapping is not yet present.
Fix addruart to use the ARM Main ID cp15 register to determine
if the core is Cortex A15 (EXYNOS5) or not (EXYNOS4).
Signed-off-by: Colin Cross <ccross@android.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch fixes missing mach-s3c24xx/common.h which has been
lost when regarding s3c24xx directories merged.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From Tony Lindgren:
Note that this also contains a set of fixes that are not regressions
or oopses to properly deal with the smsc911x regulator issue.
Basically the regulators must be per board file as the regulators
can also come from drivers, such as twl4030. So it's best to dumb
down gpmc-smsc911x.c to not even care about the regulators.
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: fix section mismatches in usb-host.c
ARM: OMAP2+: Fix omap2+ build error
ARM: OMAP2+: smsc911x: Add fixed board regulators
ARM: OMAP2+: smsc911x: Remove regulator support from gmpc-smsc911x
ARM: OMAP2+: smsc911x: Remove unused rate calculation
ARM: OMAP2+ smsc911x: Fix possible stale smsc911x flags
ARM: OMAP2+: smsc911x: Remove odd gpmc_cfg/board_data redirection
ARM: OMAP3+: fix oops triggered in omap_prcm_register_chain_handler(v1)
ARM: OMAP2+: OPP: allow OPP enumeration to continue if device is not present
arm: omap3: pm34xx.c: Replace printk() with appropriate pr_*()
arm: omap3: pm34xx.c: Fix omap3_pm_init() error out paths
ARM: OMAP4: Workaround the OCP synchronisation issue with 32K synctimer.
ARM: OMAP4: prm: fix interrupt register offsets
ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get rid of hardcoded SYSC_TYPE2_SOFTRESET_MASK
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into fixes
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This patch fixes the oops below[1].
Obviously, the count of "struct irq_chip_generic" instances to be
allocated and setup should be irq_setup->nr_regs instead of
irq_setup->nr_regs plus one, so just fix the iterator to avoid
the oops.
[1], oops log.
[ 1.790242] Unable to handle kernel NULL pointer dereference at virtual address 00000004
[ 1.798632] pgd = c0004000
[ 1.801638] [00000004] *pgd=00000000
[ 1.805400] Internal error: Oops: 805 [#1] PREEMPT SMP THUMB2
[ 1.811381] Modules linked in:
[ 1.814601] CPU: 1 Not tainted (3.3.0-next-20120320+ #733)
[ 1.820683] PC is at irq_setup_generic_chip+0x6a/0x84
[ 1.825951] LR is at irq_get_irq_data+0x7/0x8
[ 1.830508] pc : [<c006465e>] lr : [<c0063a03>] psr: 20000133
[ 1.830512] sp : ee04ff58 ip : 00000000 fp : 00000000
[ 1.842461] r10: 00000000 r9 : 00000000 r8 : 00000800
[ 1.847905] r7 : c064e260 r6 : 000001dc r5 : 00000001 r4 : ee0accc0
[ 1.854687] r3 : 00000002 r2 : 00000800 r1 : 000001dc r0 : 00000000
[ 1.861472] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment kernel
[ 1.869234] Control: 50c5387d Table: 8000404a DAC: 00000015
[ 1.875215] Process swapper/0 (pid: 1, stack limit = 0xee04e2f8)
[ 1.881463] Stack: (0xee04ff58 to 0xee050000)
[ 1.886017] ff40: c061b668 00000008
[ 1.894497] ff60: c0682090 ee0accc0 00000003 c001c637 00000000 00000000 00000201 00000000
[ 1.902976] ff80: 00000004 c0473820 c0473800 c0459e8d c0680ac0 c000866d 00000004 00000004
[ 1.911455] ffa0: ee04ffa8 00000004 c047381c 00000004 c0473820 c0473800 c0680ac0 00000082
[ 1.919934] ffc0: c0489694 c045265f 00000004 00000004 c0452135 c000d105 00000033 00000000
[ 1.928413] ffe0: c04525b5 c000d111 00000033 00000000 00000000 c000d111 aaaaaaaa aaaaaaaa
[ 1.936912] [<c006465e>] (irq_setup_generic_chip+0x6a/0x84) from [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0)
[ 1.948516] [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0) from [<c000866d>] (do_one_initcall+0x65/0xf4)
[ 1.959500] [<c000866d>] (do_one_initcall+0x65/0xf4) from [<c045265f>] (kernel_init+0xab/0x138)
[ 1.968529] [<c045265f>] (kernel_init+0xab/0x138) from [<c000d111>] (kernel_thread_exit+0x1/0x6)
[ 1.977632] Code: f7ff f9d1 6b23 1af3 (6043) 086d
[ 1.982684] ---[ end trace 1b75b31a2719ed1c ]---
[ 1.987526] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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On platforms such as OMAP3, certain variants may not have IVA, SGX
or some specific component. We currently have a check to aid fixing
wrong population of OPP entries for issues such as typos. This however
causes a conflict with valid requirement where the SoC variant does
not actually have the module present.
So, reduce the severity of the print to a debug statement and skip
registering that specific OPP, but continue down the list.
Reported-by: Steve Sakoman <steve@sakoman.com>
Reported-by: Maximilian Schwerin <mvs@tigris.de>
Acked-by: Steve Sakoman <steve@sakoman.com>
Tested-by: Maximilian Schwerin <mvs@tigris.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Currently, pm34xx.c has a mix of printk() and pr_*() statements
so replace the printk() statements with the equivalent pr_*()
statements.
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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It appears that the error paths were overlooked when the
omap3_pm_init() routine had the prcm chain handler code
added. Fix this by adding a goto target and reordering
the error handling code. Also fix how the irq argument
for free_irq() is determined.
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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On OMAP4, recently a synchronisation bug is discovered by hardware
team, which leads to incorrect timer value read from 32K sync timer
IP when the IP is comming out of idle.
The issue is due to the synchronization methodology used in the SYNCTIMER IP.
The value of the counter register in 32kHz domain is synchronized to the OCP
domain register only at count up event, and if the OCP clock is switched off,
the OCP register gets out of synch until the first count up event after the
clock is switched back -at the next falling edge of the 32kHz clock.
Further investigation revealed that it applies to gptimer1 and watchdog timer2
as well which may run on 32KHz. This patch fixes the issue for all the
applicable modules.
The BUG has not made it yet to the OMAP errata list and it is applicable to
OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps.
By enabling static depedency of wakeup clockdomain with MPU, as soon as MPU
is woken up from lowpower state(idle) or whenever MPU is active, PRCM forces
the OCP clock to be running and allow the counter value to be updated properly
in the OCP clock domain.
The bug is going to fixed in future OMAP versions.
Reported-Tested-by: dave.long@linaro.org
[dave.long@linaro.org: Reported the oprofile time stamp issue with synctimer
and helped to test this patch]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Initialize fixed regulators in the board files. Trying to
do this in a generic way in gpmc-smsc911x.c gets messy as
the regulator may be provided by drivers, such as twl4030,
for some boards.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
[tony@atomide.com: combined into one patch, updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Adding in support for regulators here creates several headaches.
- Boards that declare their own regulator cannot use this function.
- Multiple calls to this function require special handling.
- Boards that declare id's other than '0' need special handling.
Now that there is a simple regulator_register_fixed, we can push
this registration back into the board files.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Looking back into git history, this code was never used and was
probably left over from a copy/paste.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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If this function is called the first time with flags set, and the
second time without flags set then the leftover flags from the first
called will be used rather than the desired default flags.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This seems to be a leftover from when gpmc-smsc911x.c was copied
from gpmc-smc91x.c.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Fix the below section mismatch warning and alike:
WARNING: vmlinux.o(.text+0x281d4): Section mismatch in reference from
the function setup_ehci_io_mux() to the function
.init.text:omap_mux_init_signal()
The function setup_ehci_io_mux() references
the function __init omap_mux_init_signal().
This is often because setup_ehci_io_mux lacks a __init
annotation or the annotation of omap_mux_init_signal is wrong.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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With CONFIG_OMAP4_ERRATA_I688 enabled, omap2+ build
was broken as below:
arch/arm/kernel/io.c: In function '_memcpy_toio':
arch/arm/kernel/io.c:29: error: implicit declaration of function 'outer_sync'
make[1]: *** [arch/arm/kernel/io.o] Error 1
This was caused by commit 9f97da78 (Disintegrate asm/system.h for ARM).
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Previous code used wrong instance for the interrupt register access.
Use the right one which is OCP_SOCKET.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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