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* genirq: Cleanup irq_chip->typename leftoversThomas Gleixner2010-09-231-3/+3
| | | | | | | | | | | | 3 years transition phase is enough. Cleanup the last users and remove the cruft. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Leo Chen <leochen@broadcom.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Chris Zankel <chris@zankel.net>
* Merge branch 's5p-fixes-for-linus' of ↵Linus Torvalds2010-09-199-66/+107
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung * 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410 ARM: S3C64XX: Fix coding style errors on mach-real6410 ARM: S3C64XX: Prototype SPI devices ARM: S3C64XX: Fix dev-spi build ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr ARM: SAMSUNG: Fix on drive strength value ARM: S5PV210: Add FIMC clocks ARM: S5PV210: Reduce the iodesc length of systimer ARM: S5PV210: Update I2C-1 Clock Register Property. ARM: S5P: Decrease IO Registers memory region size on FIMC ARM: S5P: Fix DMA coherent mask for FIMC
| * ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410Darius Augulis2010-09-181-1/+1
| | | | | | | | | | | | | | | | | | Add IORESOURCE_IRQ_HIGHLEVEL irq flag to dm9000 driver platform data in board mach-real6410. Signed-off-by: Darius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Fix coding style errors on mach-real6410Darius Augulis2010-09-181-52/+52
| | | | | | | | | | | | | | | | Fix errors reported by checkpatch.pl script Signed-off-by: Darius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Prototype SPI devicesMark Brown2010-09-181-0/+1
| | | | | | | | | | | | | | Avoids build warnings due to the undeclared non-statics. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Fix dev-spi buildMark Brown2010-09-141-1/+1
| | | | | | | | | | | | | | | | The irqs.h usage here got missed in the Samsung platform reorganisation. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstrKukjin Kim2010-09-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes bug on gpio drive strength helper function. The offset should be like follwoing. - off = chip->chip.base - pin; + off = pin - chip->chip.base; In the s5p_gpio_get_drvstr(), the second line is unnecessary, because overwrite drvstr. drvstr = __raw_readl(reg); - drvstr = 0xffff & (0x3 << shift); And need 2bit masking before return the drvstr value. drvstr = drvstr >> shift; + drvstr &= 0x3; In the s5p_gpio_set_drvstr(), need relevant bit clear. tmp = __raw_readl(reg); + tmp &= ~(0x3 << shift); tmp |= drvstr << shift; Reported-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: SAMSUNG: Fix on drive strength valueKukjin Kim2010-09-141-5/+5
| | | | | | | | | | | | | | | | | | | | This patch fixes on defined drive strength value for GPIO. According to data sheet, if we want drive strength 1x, the value should be 00(b), if 2x should be 10(b), if 3x should be 01(b), and if 4x should be 11(b). Also fixes comment(from S5C to S5P). Reported-by: Janghyuck Kim <janghyuck.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Add FIMC clocksMarek Szyprowski2010-09-141-0/+18
| | | | | | | | | | | | | | | | | | | | These clocks enables FIMC driver to operate on machines, which bootloader power gated FIMC devices to save power on boot. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Reduce the iodesc length of systimerKyungmin Park2010-09-141-1/+1
| | | | | | | | | | | | | | It's enough to use 4KiB. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Update I2C-1 Clock Register Property.MyungJoo Ham2010-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | CLK_GATE_IP3[8] is RESERVED. The port "I2C_HDMI_DDC" of CLK_GATE_IP3[10] is used as another I2C port. Therefore, defined the unused I2C-1 as another I2C there was left undefined but used. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5P: Decrease IO Registers memory region size on FIMCSylwester Nawrocki2010-09-143-3/+3
| | | | | | | | | | | | | | | | | | | | | | IO registers region size of all FIMC versions is less than 1kB so there is no need to reserve 1M. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5P: Fix DMA coherent mask for FIMCMarek Szyprowski2010-09-143-0/+21
| | | | | | | | | | | | | | | | | | | | FIMC driver uses DMA_coherent allocator, which requires proper dma mask to be set. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | arm: fix really nasty sigreturn bugAl Viro2010-09-171-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a signal hits us outside of a syscall and another gets delivered when we are in sigreturn (e.g. because it had been in sa_mask for the first one and got sent to us while we'd been in the first handler), we have a chance of returning from the second handler to location one insn prior to where we ought to return. If r0 happens to contain -513 (-ERESTARTNOINTR), sigreturn will get confused into doing restart syscall song and dance. Incredible joy to debug, since it manifests as random, infrequent and very hard to reproduce double execution of instructions in userland code... The fix is simple - mark it "don't bother with restarts" in wrapper, i.e. set r8 to 0 in sys_sigreturn and sys_rt_sigreturn wrappers, suppressing the syscall restart handling on return from these guys. They can't legitimately return a restart-worthy error anyway. Testcase: #include <unistd.h> #include <signal.h> #include <stdlib.h> #include <sys/time.h> #include <errno.h> void f(int n) { __asm__ __volatile__( "ldr r0, [%0]\n" "b 1f\n" "b 2f\n" "1:b .\n" "2:\n" : : "r"(&n)); } void handler1(int sig) { } void handler2(int sig) { raise(1); } void handler3(int sig) { exit(0); } main() { struct sigaction s = {.sa_handler = handler2}; struct itimerval t1 = { .it_value = {1} }; struct itimerval t2 = { .it_value = {2} }; signal(1, handler1); sigemptyset(&s.sa_mask); sigaddset(&s.sa_mask, 1); sigaction(SIGALRM, &s, NULL); signal(SIGVTALRM, handler3); setitimer(ITIMER_REAL, &t1, NULL); setitimer(ITIMER_VIRTUAL, &t2, NULL); f(-513); /* -ERESTARTNOINTR */ write(1, "buggered\n", 9); return 1; } Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: stable@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91Linus Torvalds2010-09-104-19/+36
|\ | | | | | | | | | | | | | | | | | | * 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91: AT91: at91sam9261ek: remove C99 comments but keep information AT91: at91sam9261ek board: remove warnings related to use of SPI or SD/MMC AT91: dm9000 initialization update AT91: SAM9G45 - add a separate clock entry for every single TC block AT91: clock: peripheral clocks can have other parent than mck AT91: change dma resource index
| * AT91: at91sam9261ek: remove C99 comments but keep informationNicolas Ferre2010-09-101-4/+2
| | | | | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: at91sam9261ek board: remove warnings related to use of SPI or SD/MMCNicolas Ferre2010-09-101-11/+19
| | | | | | | | | | | | | | | | | | The sd/mmc data structure is not used if SPI is selected. The configuration of PIO on the board prevent from using both interfaces at the same time (board dependent). Remove the warnings at compilation time adding a preprocessor condition. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: dm9000 initialization updateNicolas Ferre2010-09-101-1/+2
| | | | | | | | | | | | | | | | Add information in dm9000 mac/phy chip initialization: - irq resource details - platform data details Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: SAM9G45 - add a separate clock entry for every single TC blockFabian Godehardt2010-09-092-5/+14
| | | | | | | | | | | | | | | | | | | | | | Without this patch you will not be able to register the first block because of the second association call on at91_add_device_tc(). Signed-off-by: Fabian Godehardt <fg@emlix.com> [nicolas.ferre@atmel.com: change tcb1_clk to fake child clock of tcb0_clk] Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: clock: peripheral clocks can have other parent than mckNicolas Ferre2010-09-091-1/+2
| | | | | | | | | | | | | | | | | | | | While registering clock allow to set parent clock other than mck. It is useful for clocks than can be seen as child clock of a peripheral. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za>
| * AT91: change dma resource indexNicolas Ferre2010-09-071-1/+1
| | | | | | | | | | Reported-by: Dan Liang <dan.liang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | ARM: Update mach-typesRussell King2010-09-091-2/+96
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: Partially revert "Auto calculate ZRELADDR and provide option for ↵Russell King2010-09-094-95/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | exceptions" Partially revert e69edc7, which introduced automatic zreladdr support. The change in the way the manual definition is defined seems to be error and conflict prone. Go back to the original way we were handling this for the time being, while keeping the automatic zreladdr facility. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'origin'Russell King2010-09-091-0/+1
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| * | [ARM] tegra: Add ZRELADDR default for ARCH_TEGRAErik Gilling2010-09-011-0/+1
| |/ | | | | | | | | | | | | | | | | fixes the warning: .config:369:warning: symbol value '' invalid for ZRELADDR and the prompt for ZRELADDR on make Signed-off-by: Erik Gilling <konkers@android.com>
* | ARM: Ensure PTE modifications via dma_alloc_coherent are visibleRussell King2010-09-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dave Hylands reports: | We've observed a problem with dma_alloc_writecombine when the system | is under heavy load (heavy bus traffic). We've managed to reduce the | problem to the following snippet, which is run from a kthread in a | continuous loop: | | void *virtAddr; | dma_addr_t physAddr; | unsigned int numBytes = 256; | | for (;;) { | virtAddr = dma_alloc_writecombine(NULL, | numBytes, &physAddr, GFP_KERNEL); | if (virtAddr == NULL) { | printk(KERN_ERR "Running out of memory\n"); | break; | } | | /* access DMA memory allocated */ | tmp = virtAddr; | *tmp = 0x77; | | /* free DMA memory */ | dma_free_writecombine(NULL, | numBytes, virtAddr, physAddr); | | ...sleep here... | } | | By itself, the code will run forever with no issues. However, as we | increase our bus traffic (typically using DMA) then the *tmp = 0x77 | line will eventually cause a page fault. If we add a small delay (a | few microseconds) before the *tmp = 0x77, then we don't see a page | fault, even under heavy load. A dsb() is required after modifying the PTE entries to ensure that they will always be visible. Add this dsb(). Reported-by: Dave Hylands <dhylands@gmail.com> Tested-by: Dave Hylands <dhylands@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6359/1: ep93xx: move clock initialization earlierMika Westerberg2010-09-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7cfe24947 ("ARM: AMBA: Add pclk support to AMBA bus infrastructure") changed AMBA bus to handle the PCLK automatically. However, in EP93xx clock initialization is arch_initcall which is done later than AMBA device identification. This causes amba_get_enable_pclk() to fail resulting device where UARTs are not functional. So change ep93xx_clock_init() to be postcore_initcall. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Revert "[ARM] pxa: remove now unnecessary dma_needs_bounce()"Russell King2010-09-082-8/+8
| | | | | | | | | | | | | | | | | | This reverts commit 4fa5518, which causes a compilation regression for IXP4xx platforms. Reported-by: Richard Cochran <richardcochran@gmail.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6352/1: perf: fix event validationWill Deacon2010-09-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The validate_event function in the ARM perf events backend has the following problems: 1.) Events that are disabled count towards the cost. 2.) Events associated with other PMUs [for example, software events or breakpoints] do not count towards the cost, but do fail validation, causing the group to fail. This patch changes validate_event so that it ignores events in the PERF_EVENT_STATE_OFF state or that are scheduled for other PMUs. Reported-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6344/1: Mark CPU_32v6K as depended on CPU_V7Catalin Marinas2010-09-021-1/+1
| | | | | | | | | | | | | | | | CPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'imx-for-2.6.36' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2010-09-019-33/+68
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| * | ARM: imx: set cache line size to 64 bytes for i.MX5Jason Wang2010-08-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core of i.MX5 series is cortex-A8, its cache line size is 64 bytes instead of 32 bytes. Refer to the OMAP3's selection, we choose 64 bytes for i.MX5, this can increase a little bit performance when perform cache operations. Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mx5/clock: fix clear bit fields issue in _clk_ccgr_disable functionJason Wang2010-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can see MXC_CCM_CCGRx_MOD_OFF is defined as 0 while MXC_CCM_CCGRx_CG_MASK is defined as 0x3 in crm_regs.h, here in the _clk_ccgr_disable function, we want to clear the corresponding enable bit fields to disable this clock, so we should choose MASK instead of OFF otherwise clocks can't be disabled. Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mxc/tzic: add base address when accessing TZIC registersJason Wang2010-08-211-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we call tzic_enable_wake function, the kernel will crash because of access to an unmapped address. This is because two register access operations forgot to add base address. Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clock-imx35: Calculate the base clock rate for the IPU unitJuergen Beisert2010-08-171-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mx3fb driver needs the clock the IPU runs in order to calculate the divider for the LCD clock. This patch adds the clock rate calculation routine for the i.MX35 CPU. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clock-imx35: correct arm and ahb clock calculationMarc Kleine-Budde2010-08-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Datasheet: "i.MX35 (MCIMX35) Multimedia Applications Processor Reference Manual, Rev. 2" "Figure 14-24. Clock Control And Gating" change the result of get_rate_ahb based on the frequency returned by get_rate_arm to calculate the proper rate. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clock-imx35: fix divider if ahb is source for ipg_perMarc Kleine-Budde2010-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Datasheet: "i.MX35 (MCIMX35) Multimedia Applications Processor Reference Manual, Rev. 2" "Table 14-6. PDR0 Field Descriptions" the divider is CCM_PER_AHB[3:0] + 1. This patch adds the missing + 1. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | i.MX35: remove get_3_3_div helper functionSascha Hauer2010-08-171-15/+9
| | | | | | | | | | | | | | | | | | | | | | | | In the v2 reference manual there are no dividers combined of two dividers. Instead, all dividers are simple 6bit dividers. I assume the combined dividers only exist in preliminary hardware. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mx35: Fix boot ROM hang in internal boot modeHans J. Koch2010-08-171-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a watchdog reset occurs after booting in internal boot mode, the i.MX35 won't boot anymore. The boot ROM code seems to assume that some clocks are turned on (they are after a power-on reset). This patch turns on the necessary clocks. Signed-off-by: Hans J. Koch <hjk@linutronix.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reported-by: John Ogness <jogness@linutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | eukrea-baseboards: fix the merge in one fileEric Bénard2010-08-165-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Last change I did made a big mess in function names and CONFIG names, this patch fixes this so that the baseboard support is really built when selected. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'fix' of ↵Russell King2010-09-014-5/+5
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| * | | ARM: pxa: Make id const in pwm_probe()Uwe Kleine-König2010-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the compiler warning: arch/arm/plat-pxa/pwm.c: In function 'pwm_probe': arch/arm/plat-pxa/pwm.c:179: warning: initialization discards qualifiers from pointer target type Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | ARM: pxa: fix CI_HSYNC and CI_VSYNC MFP defines for pxa300Axel Lin2010-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to PXA3xx Processor Family Developer Manuall Vol1. section "Pin Descriptions and Control", PXA30x and PXA31x Processor Alternate Function Table shows the Alt FN 0 for GPIO51 is CI_HSYNC and for GPIO52 is CI_VSYNC. This patch fixes the MFP defines and also corrects the order of MFD defines. Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | ARM: pxa: remove __init from cpufreq_driver->init()Eric Miao2010-08-302-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | This is causing section mismatches when linking, as cpufreq_driver->init() is not supposed to be in init section. Reported-by: Tomáš 'Sleep_Walker' Čech <sleep_walker@suse.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* | | Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6Russell King2010-09-015-20/+220
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| * | | ARM: mach-shmobile: ap4evb: fix write protect for SDHI1Arnd Hannemann2010-08-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDHI1 on AP4EVB has no pin to detect write protection of a card. This had the result that a card inserted in this slot was always detected as read only. This patch adds the corresponding flag to disable write protection detection for SDHI1. Signed-off-by: Arnd Hannemann <arnd@arndnet.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | ARM: mach-shmobile: ap4evb: modify FSI2 IDKuninori Morimoto2010-08-181-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | ARM: mach-shmobile: do not enable the PLLC2 clock on initGuennadi Liakhovetski2010-08-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP4EVB has to reparent PLLC2 to provide a precise HDMI clock, this is only possible, if PLLC2 hasn't been enabled yet. Since no other driver currently uses PLLC2 we can safely remove the CLK_ENABLE_ON_INIT flag. This fixes the "Cannot set PLLC2 parent: -16, 1 users" error message, when trying to use HDMI on AP4EVB. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | ARM: mach-shmobile: Clock framework comment fixMagnus Damm2010-08-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update clock framework header comment for SH-Mobile ARM. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | ARM: mach-shmobile: Fix up gpio-leds pdata definition.Paul Mundt2010-08-161-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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