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* flagday: don't pass regs to copy_thread()Al Viro2012-11-281-2/+1
| | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* arm64: sanitize copy_thread(), switch to generic fork/vfork/cloneAl Viro2012-11-281-4/+4
| | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* Merge commit '6ba1bc826d160fe4f32bcb188687dcca4bdfaf3d' into arch-arm64Al Viro2012-11-161-18/+0
|\ | | | | | | | | | | | | | | Backmerge from mainline commit that introduced a trivial conflict in arch/arm64/kernel/process.c - a bunch of functions removed next to the place where kernel_thread() used to be. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
| * arm64: elf: fix core dumping definitions for GP and FP registersWill Deacon2012-11-081-18/+0
| | | | | | | | | | | | | | | | | | | | struct user_fp does not exist for arm64, so use struct user_fpsimd_state instead for the ELF core dumping definitions. Furthermore, since we use regset-based core dumping, we do not need definitions for dump_task_regs and dump_fpu. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | arm64: get rid of fork/vfork/clone wrappersAl Viro2012-10-221-2/+8
| | | | | | | | | | | | | | | | [fixes from Catalin Marinas folded] Acked-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | arm64: Use generic kernel_thread() implementationCatalin Marinas2012-10-171-53/+24
|/ | | | | | | | | This patch enables CONFIG_GENERIC_KERNEL_THREAD on arm64, changes copy_threads to cope with kernel threads creation and adapts ret_from_fork accordingly. The arm64-specific kernel_thread implementation is no longer needed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Process managementCatalin Marinas2012-09-171-0/+408
The patch adds support for thread creation and context switching. The context switching CPU specific code is introduced with the CPU support patch (part of the arch/arm64/mm/proc.S file). AArch64 supports ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable via the ID_AA64AFR0_EL1 register). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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