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* arm64: dts: Fix various entry-method properties to reflect documentationAmit Kucheria2018-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Fix the cpu-capacity.txt documentation that uses the incorrect value so we don't get copy-paste errors like these. Clarify the language in idle-states.txt by removing the reference to the psci bindings that might be causing this confusion. Finally, fix devicetrees of various boards to reflect current documentation. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm64: zynqmp: Add SPDX license identifierMichal Simek2018-02-231-0/+1
| | | | | | | | Add SPDX identifier as was done by for example by: "License cleanup: add SPDX GPL-2.0 license identifier to files with no license" (commit <b24413180f5600bcb3bb70fbed5cf186b60864bd>) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Fix alignment in dts filesMichal Simek2018-02-231-4/+4
| | | | | | Trivial changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Use zynqmp specific compatible string for macbMichal Simek2018-02-231-4/+4
| | | | | | | | | | The patch "devicetree: Add compatible string for Zynq Ultrascale+ MPSoC" (commit <988d6f07fc0a29e392035ba56e3bcfaf7b397d95>) introduced specific compatible string for ZynqMP which should be used first. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add fpd/lpd dmasMichal Simek2017-08-211-0/+165
| | | | | | Wire fpd and lpd dma channels to zynqmp.dtsi. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Set status disabled in dtsiNaga Sureshkumar Relli2017-08-211-0/+1
| | | | | | | Do not enable smmu via dtsi. Enable it in board file when needed. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add new uartps compatible stringMichal Simek2017-08-211-2/+2
| | | | | | | | | | Mainline kernel has r1p12 compatible string now. Use this new compatible string and also append generic compatible string. Keep in your mind that using this generic compatible string not all uart features will be available. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org>
* arm64: zynqmp: Correct IRQ nr for the SMMUEdgar E. Iglesias2017-08-211-5/+5
| | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add support for RTCMichal Simek2017-08-211-0/+10
| | | | | | Add support for RTC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Adding prefetchable memory space to pcie nodeBharat Kumar Gogada2017-08-211-6/+2
| | | | | | | | | | Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add CCI-400 nodeMichal Simek2017-08-211-0/+19
| | | | | | Add CCI-400 node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add dcc console for zynqmpMichal Simek2017-08-211-0/+5
| | | | | | | | | | Add debug console to dtsi to be able to enable it in board dts file. Keep in your mind that every core has separate dcc port in case you want to run SMP kernel. DCC is very helpful communication channel for debugging. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add operating pointsShubhrajyoti Datta2017-08-211-0/+29
| | | | | | | Adding operating-points-v2 for zynqmp. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add idle state for ZynqMPStefan Krsmanovic2017-08-211-0/+17
| | | | | | | | | | | | Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0 idle state is added in this patch. References to the idle-states node are added in all CPU nodes. Time values: entry/exit latencies and min-residency, needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0 and Extended StateID format. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add references to cpu nodesMichal Simek2017-08-211-4/+4
| | | | | | | Add missing references to all cpu nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org>
* arm64: dts: xilinx: fix PCI bus dtc warningsRob Herring2017-07-201-0/+1
| | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Fix i2c node's compatible stringMoritz Fischer2017-01-021-2/+2
| | | | | | | | | | | | | The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Fix W=1 dtc 1.4 warningsMichal Simek2017-01-021-1/+1
| | | | | | | | | | The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann2016-09-141-4/+4
|\ | | | | | | | | | | | | | | * dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
| * arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier2016-09-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | ARM64: zynqmp: Correct the watchdog timer interrupt numberPunnaiah Choudary Kalluri2016-08-191-1/+1
| | | | | | | | | | | | | | | | Corrected the watchdog timer interrupt number. Origin value was for CSUPMU watchdog. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add missing interrupt-parent to PMU nodeMichal Simek2016-08-191-0/+1
| | | | | | | | | | | | | | | | | | ZynqMP is not using global interrupt-parent setting that's why it has to be listed in every node separately. PMU node missed it and this patch is adding it. Reported-by: John Linn <John.Linn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add PCIe nodeMichal Simek2016-08-191-0/+39
| | | | | | | | | | | | | | Add PCIe node with prefetchable memory which goes beyond 4GB. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Use 64bit size cell formatMichal Simek2016-08-191-27/+27
| | | | | | | | | | | | | | Use 64bit size cell format instead of 32bit for memory description. Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Align gic ranges for 64k in device treeAlexander Graf2016-08-191-2/+2
|/ | | | | | | | | | | | | The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Extract clock information from EP108Michal Simek2016-02-251-42/+1
| | | | | | | Extract clocks and put it specific file to help with platform autogeneration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Keep gpio node alphabetically sortedMichal Simek2016-02-251-12/+12
| | | | | | No functional change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: DT: Add interrupt-controller property to GPIOSoren Brinkmann2015-12-141-0/+2
| | | | | | | | GPIO can be used as interrupt-controller. Add the missing properties to the GPIO node. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Move SPI nodes to the right locationMichal Simek2015-07-311-24/+24
| | | | | | Keep nodes sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Move uart and ttcs to the right locationMichal Simek2015-07-311-60/+60
| | | | | | Sort nodes in DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add DWC3 usb supportMichal Simek2015-07-311-0/+20
| | | | | | Add usb nodes to DTSI and enable both of them on ep108. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add SMMU supportMichal Simek2015-07-311-0/+12
| | | | | | Add SMMU DT node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add CANs node for platformMichal Simek2015-07-311-0/+24
| | | | | | Also enable can0 for ep108. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Use zynqmp specific compatible string for gpioMichal Simek2015-07-311-1/+1
| | | | | | | | | | | The patch: "gpio: Added support to Zynq Ultrascale+ MPSoC" (sha1: bdf7a4ae371894b4dc10b5820006b0a82d484929) added zynqmp specific features. This patch is switching the driver to use the zynqmp compatible string. Also enable the driver for ep108 platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* devicetree: xilinx: zynqmp: add sata nodeSuneel Garapati2015-07-311-0/+15
| | | | | | | | add sata node with sata fixed clock nodes in dtsi file. enable sata in zynqmp-ep108.dts with broken-gen2. Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: Add new Xilinx ZynqMP SoCMichal Simek2015-03-111-0/+305
Initial version of device tree for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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