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* kbuild: clean up *.dtb and *.dtb.S patterns from top-level MakefileMasahiro Yamada2017-11-081-1/+0
| | | | | | | | | | | | We need to add "clean-files" in Makfiles to clean up DT blobs, but we often miss to do so. Since there are no source files that end with .dtb or .dtb.S, so we can clean-up those files from the top-level Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Herring <robh@kernel.org>
* Merge tag 'armsoc-devicetree' of ↵Linus Torvalds2017-09-1012-43/+780
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM/arm64 Devicetree updates from Olof Johansson: "As usual, device tree updates is the bulk of our material in this merge window. This time around, 559 patches affecting both 32- and 64-bit platforms. Changes are too many to list individually, but some of the larger ones: New platform/SoC support: - Automotive: + Renesas R-Car D3 (R8A77995) + TI DT76x + MediaTek mt2712e - Communication-oriented: + Qualcomm IPQ8074 + Broadcom Stingray + Marvell Armada 8080 - Set top box: + Uniphier PXs3 Besides some vendor reference boards for the SoC above, there are also several new boards/machines: - TI AM335x Moxa UC-8100-ME-T open platform - TI AM57xx Beaglebone X15 Rev C - Microchip/Atmel sama5d27 SoM1 EK - Broadcom Raspberry Pi Zero W - Gemini-based D-Link DIR-685 router - Freescale i.MX6: + Toradex Apalis module + Apalis and Ixora carrier boards + Engicam GEAM6UL Starter Kit - Freescale i.MX53-based Beckhoff CX9020 Embedded PC - Mediatek mt7623-based BananaPi R2 - Several Allwinner-based single-board computers: + Cubietruck plus + Bananapi M3, M2M and M64 + NanoPi A64 + A64-OLinuXino + Pine64 - Rockchip RK3328 Pine64/Rock64 board support - Rockchip RK3399 boards: + RK3399 Sapphire module on Excavator carrier (RK3399 reference design) + Theobroma Systems RK3399-Q7 SoM - ZTE ZX296718 PCBOX Board" * tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits) ARM: dts: at91: at91sam9g45: add AC97 arm64: dts: marvell: mcbin: enable more networking ports arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node arm64: dts: marvell: add TX interrupts for PPv2.2 arm64: dts: uniphier: add PXs3 SoC support ARM: dts: uniphier: add pinctrl groups of ethernet phy mode ARM: dts: uniphier: fix size of sdctrl nodes ARM: dts: uniphier: add AIDET nodes arm64: dts: uniphier: fix size of sdctrl node arm64: dts: uniphier: add AIDET nodes Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2" arm64: dts: uniphier: add reset controller node of analog amplifier arm64: dts: marvell: add Device Tree files for Armada-8KP arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM dt-bindings: add rk3399-q7 SoM ARM: dts: rockchip: enable usb for rv1108-evb ARM: dts: rockchip: add usb nodes for rv1108 SoCs dt-bindings: update grf-binding for rv1108 SoCs ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers ...
| * arm64: dts: marvell: mcbin: enable more networking portsAntoine Tenart2017-08-301-0/+30
| | | | | | | | | | | | | | | | | | | | This patch enables the two GE/SFP ports. They are configured in 10GKR mode by default. To do this the cpm_xdmio is enabled as well, and two phy descriptions are added. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 nodeAntoine Tenart2017-08-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | The network driver on Marvell SoC (7k/8k) needs to access some registers in the system controller to configure its ports at runtime. This patch adds a phandle reference to the syscon system controller node in the ppv2 node. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: add TX interrupts for PPv2.2Thomas Petazzoni2017-08-302-6/+42
| | | | | | | | | | | | | | | | | | This commit updates the Marvell Armada 7K/8K Device Tree to describe the TX interrupts of the Ethernet controllers, in both the master and slave CP110s. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: add Device Tree files for Armada-8KPHanna Hawa2017-08-245-0/+388
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the base Device Tree files for the Armada 8KPlus. The Armada 8KP SoCs include several hardware blocks, and this commit only adds support for the AP810 block, that contains the CPU core and basic peripherals. AP810 is a high-performance die, includes octal core application processor based ARMv8-A architecture, two standard high speed DDR4 interface, and GIC-600 interrupt controller. AP810 Built as part of Marvell’s MoChi AP family products. Armada-8080 (8KPlus family), include an AP810 block that contains the CPU core and basic peripherals. This commit creates the following hierarchy: * armada-ap810-ap0.dtsi - definitions common to AP810 * armada-ap810-ap0-octa-core.dtsi - description of the octa cores * armada-8080.dtsi - description of the 8080 SoC * armada-8080-db.dts - description of the 8080 board Signed-off-by: Hanna Hawa <hannah@marvell.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: enable USB host on Armada-8040-DBGrzegorz Jaszczyk2017-08-141-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable USB host on Armada-8040-DB by adding USB PHY nodes for the following ports: - host 0 and 1 of CPM - host 0 of CPS These PHY are enabled by lanes coming from regulators based on two I2C expanders. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: enable USB host on Armada-7040-DBHanna Hawa2017-08-141-0/+39
| | | | | | | | | | | | | | | | | | Add I2C expander and USB host PHY (host 0 and host 1) to enable USB VBUS on USB ports of type A on Armada-7040-DB. Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: add NAND support on the CP110Gregory CLEMENT2017-08-142-0/+30
| | | | | | | | | | | | | | | | | | | | The NAND controller used in A7K/A8K is present on the CP110. It is compatible with the pxa-nand driver. However, due to the limiation of the pins available this controller is only usable on the CPM for A7K and on the CPS for A8K. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: armada-37xx: Enable uSD on ESPRESSObinMarcin Wojtas2017-08-031-0/+25
| | | | | | | | | | | | | | | | | | | | | | The ESPRESSObin board exposes one of the SDHCI interfaces via J1 uSD slot. This patch enables it. Tested-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Zbigniew Bodek <zbodek@gmail.com> [gregory.clement@free-electrons.com: removed "no-1-8-v"] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: Fully re-order nodes in Marvell CP110 dtsi filesGregory CLEMENT2017-08-032-18/+18
| | | | | | | | | | | | | | | | Since the introduction of the CP110 dt files, the sata node was misplaced. Move it at the right place. Thanks to this, the files are completely ordered. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: re-order RTC nodes in Marvell CP110 descriptionThomas Petazzoni2017-08-022-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | In both the CP110 master and slave description, the node describing the RTC was at the wrong place when taking into account increasing register addresses. Interestingly, it was not even at the same (wrong) place in both files. This commit adjusts that, making the master and slave descriptions more aligned. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: mcbin: add an stdout-pathAntoine Tenart2017-08-021-0/+4
| | | | | | | | | | | | | | | | This patch adds an stdout-path to the mcbin device tree. This allows to use earlycon. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: mcbin: add support for PCIeRussell King2017-08-021-0/+13
| | | | | | | | | | | | | | | | | | | | Add support for PCIe with the the PCIe reset signal wired up to the appropriate GPIO pin. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> (excepted the reset part) Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: mcbin: add support for i2c muxRussell King2017-08-021-0/+34
| | | | | | | | | | | | | | | | The MACCHIATOBin board has a PCA9548 I2C mux for the SFP ports on CP100 master I2C bus 1. Add the DT description for it. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: fix USB3 regulator definition on MacchiatoBinRussell King2017-08-021-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Due to the lack of GPIO support, the USB3 regulator definition was left unfinished in the MacchiatoBin DT description. Now that GPIO support is available, this commit adjusts the Device Tree to properly describe the USB3 regulator. [gregory.clement@free-electrons.com: use commit log from Thomas] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: mcbin: add pinctrl nodesRussell King2017-08-021-0/+31
| | | | | | | | | | | | | | Add pinctrl nodes to describe the CPM I2C0 and CPS SPI1 settings. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: cp110: add GPIO interruptsRussell King2017-08-022-2/+20
| | | | | | | | | | | | | | Add the GPIO interrupts for the CP110. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: armada-37xx: Enable USB2 on espressobinMarc Zyngier2017-08-021-0/+5
| | | | | | | | | | | | | | | | The Espressobin SBC has a USB2 interface available on J8. Let's enable it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: armada-37xx: Wire PMUv3Marc Zyngier2017-08-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | The Cortex-A53s that power the Armada-37xx SoCs are equipped with a PMUv3, just like most ARMv8 cores. Advertise the PMUv3 presence in the device tree, and wire its interrupt. This allows the perf subsystem to work correctly. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interfaceMarc Zyngier2017-08-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A53s that power the Armada-37xx SoCs are equipped with a GIC CPU interface that gets enabled when coupled with a GICv3 interrupt controller, such as the GIC-500 on the this SoC. Advertise the MMIO ranges provided by the CPUs, which enables (among other things) GICv2 guests to run under a hypervisor such as KVM. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * ARM64: dts: marvell: armada-37xx: Fix GIC maintenance interruptMarc Zyngier2017-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC-500 integrated in the Armada-37xx SoCs is compliant with the GICv3 architecture, and thus provides a maintenance interrupt that is required for hypervisors to function correctly. With the interrupt provided in the DT, KVM now works as it should. Tested on an Espressobin system. Fixes: adbc3695d9e4 ("arm64: dts: add the Marvell Armada 3700 family and a development board") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: fix number of GPIOs in Armada AP806 descriptionThomas Petazzoni2017-08-301-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | The Armada AP806 has 20 pins, and therefore 20 GPIOs (from 0 to 19 included) and not 19 pins. Therefore, we fix the Device Tree description for the GPIO controller. Before this patch: $ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges GPIO ranges handled: 0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19] 0: f06f4000.system-controller:gpio GPIOS [0 - 18] PINS [0 - 18] After this patch: $ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges GPIO ranges handled: 0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19] 0: f06f4000.system-controller:gpio GPIOS [0 - 19] PINS [0 - 19] Fixes: 63dac0f4924b9 ("arm64: dts: marvell: add gpio support for Armada 7K/8K") Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridgeGregory CLEMENT2017-08-021-1/+1
| | | | | | | | | | | The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Fixes: afda007feda5 ("ARM64: dts: marvell: Add pinctrl nodes for Armada 3700") Cc: <stable@vger.kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: mark the cp110 crypto engine as dma coherentAntoine Tenart2017-07-192-0/+2
| | | | | | | | | | The crypto engines found on the cp110 master and slave are dma coherent. This patch adds the relevant property to their dt nodes. Cc: stable@vger.kernel.org # v4.12+ Fixes: 973020fd9498 ("arm64: marvell: dts: add crypto engine description for 7k/8k") Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use ICU for the CP110 slave RTCThomas Petazzoni2017-07-181-1/+1
| | | | | | | | | | | When the conversion of the Marvell CP110 Device Tree description from using GIC interrupts to using ICU interrupts was done, the RTC on the slave CP110 was left unchanged. This commit fixes that, so that all devices on the CP properly get their interrupt through the ICU. Fixes: 6ef84a827c375 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K") Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge tag 'mvebu-dt64-4.13-3' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2017-07-031-8/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | next/dt64 Pull "late dt64 for 4.13" from Gregory CLEMENT: It is actually a patch that missed the end of the 4.12 merge window. The patch itself fix a bogus definition of the timer for the Armada 37xx SoCs. * tag 'mvebu-dt64-4.13-3' of git://git.infradead.org/linux-mvebu: ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
| * ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiersMarc Zyngier2017-07-031-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult. Fixes: adbc3695d9e4 ("arm64: dts: add the Marvell Armada 3700 family and a development board") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"Arnd Bergmann2017-06-232-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I found by chance while merging another patch, the usage of a dma-mask in this DT node is wrong for multiple reasons: - dma-masks are a Linux specific concept, not a general hardware feature - In DT, we use the "dma-ranges" property to describe how DMA addresses related between devices. - The 40-bit mask appears to be completely unnecessary here, as the SoC cannot address that much memory anyway, so simply asking for a 64-bit mask (as supported by the device) should succeed anyway. The patch to remove the parsing of the property is getting merged through the crypto tree. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | Merge tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2017-06-232-4/+2
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | next/dt64 mvebu fixes for 4.12 Fix the interrupt description of the crypto node for device tree of the Armada 7K/8K SoCs * tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu: arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes
| * arm64: marvell: dts: fix interrupts in 7k/8k crypto nodesAntoine Tenart2017-05-242-4/+2
| | | | | | | | | | | | | | | | | | The cryptographic engine nodes have an interrupt which is configured as both edge and level, which makes no sense at all. Fix this by configuring it the right way (level). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: enable GICP and ICU on Armada 7K/8KThomas Petazzoni2017-06-213-48/+73
| | | | | | | | | | | | | | | | | | This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files to describe the ICU and GICP units, and use ICU interrupts for all devices in the CP110 blocks. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add gpio support for Armada 7K/8KGregory CLEMENT2017-06-205-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs. The Armada 8K has two CP110 blocks, each having two GPIO controllers. However, in each CP110 block, one of the GPIO controller cannot be used: in the master CP110, only the second GPIO controller can be used, while on the slave CP110, only the first GPIO controller can be used. On the other side, the Armada 7K has only one CP110, but both its GPIO controllers can be used. For this reason, the GPIO controllers are marked as "disabled" in the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only enabled in the per-SoC dtsi files. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add pinctrl support for Armada 7K/8KGregory CLEMENT2017-06-207-6/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs. The CP master being different between Armada 7k and Armada 8k. This commit introduces the intermediates files armada-70x0.dtsi and armada-80x0.dtsi. These new files will provide different compatible strings depending of the SoC family. They will also be the location for the pinmux configuration at the SoC level. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: use new binding for the system controller on cp110Gregory CLEMENT2017-06-202-39/+45
| | | | | | | | | | | | | | | | | | The new binding for the system controller on cp110 moved the clock controller into a subnode. This preliminary step will allow to add gpio and pinctrl subnodes. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: remove *-clock-output-names on cp110Gregory CLEMENT2017-06-202-26/+0
| | | | | | | | | | | | | | | | The *-clock-output-names of the cp110-system-controller0 node are not used anymore, so remove them. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: use new bindings for xor clocks on ap806Antoine Tenart2017-06-201-4/+4
| | | | | | | | | | | | | | | | | | New bindings are used for the system controller on the ap806, which means all clock properties must be converted. Use the new bindings in the xor nodes. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: mcbin: enable the mdio nodeAntoine Tenart2017-06-201-0/+2
| | | | | | | | | | | | | | | | | | Since the mdio nodes are disabled by default now, we should explicitly enable these nodes at the board level when they are used. Enable the cpm_mdio node for the 8040-mcbin. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add xmdio nodes for 7k/8kAntoine Tenart2017-06-172-0/+16
| | | | | | | | | | | | | | | | | | | | Add the description of the xMDIO bus for the Marvell Armada 7k and Marvell Armada 8k; for both CP110 slave and master. This bus is found on Marvell Ethernet controllers and provides an interface with the xMDIO bus. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add a comment on the cp110 slave node statusAntoine Tenart2017-06-171-0/+7
| | | | | | | | | | | | | | | | | | The cryptographic engine found on the cp110 slave is disabled by default because of some known limitations. Add a comment to explain why it is disabled by default. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: remove cpm crypto nodes from dts filesAntoine Tenart2017-06-172-8/+0
| | | | | | | | | | | | | | | | The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: cp110: enable the crypto engine at the SoC levelAntoine Tenart2017-06-171-1/+0
| | | | | | | | | | | | | | | | | | Enable the cryptographic engine at the SoC level on the master cp110. This engine is always present and do not depends on any pinmux configuration. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slotGregory CLEMENT2017-06-171-0/+15
| | | | | | | | | | | | | | | | | | By adding this regulator, the SD cards are usable at higher speed protocols such as SDR104. This patch was tested with an SD HC card compatible with UHS-I. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: Enable second SDHCI controller in Armada 37xxKonstantin Porotchkin2017-06-172-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second one. Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces. The second interface is using pluggable module that can either have an SD connector or eMMC on it. This patch adds support for SD module in the device DT. [ gregory.clement@free-electrons.com: - Add more detail in commit log - Sort the dt node in address order - Document the SD slot in the dts ] Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-37xx: Use angle bracket for each register setGregory CLEMENT2017-06-171-4/+4
| | | | | | | | | | | | | | When several groups of register address and size are used with reg, then surround each one by angle bracket. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-37xx: Align the compatible stringGregory CLEMENT2017-06-171-3/+3
| | | | | | | | | | | | | | This cosmetic patch aligns the compatible string when there are on several lines. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-3720-db: Add information about the V2 boardGregory CLEMENT2017-06-171-4/+13
| | | | | | | | | | | | | | | | The initial device tree file was for the board V1.4. Now the V2.0 board is also available. The same dtb will work for both, but the CON number have changed, so update the comment in the dts to reflect this. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-3720-db: Sort the dts node alphabeticallyGregory CLEMENT2017-06-171-42/+41
| | | | | | | | | | | | | | | | Sort the reference nodes in alphabetical order to ease the merge of future nodes. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: disable the mdio nodes by defaultAntoine Tenart2017-06-172-0/+2
| | | | | | | | | | | | | | | | Disable the mdio nodes by default in the cp110 slave and master dtsi as they're not wired on every board. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DBAntoine Tenart2017-06-172-0/+6
| | | | | | | | | | | | | | | | | | Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell Armada 8k DB. This is needed as the MDIO nodes will be disabled in the CP 110 slave and master dtsi by a following up patch. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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