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* arm64: dts: juno: add coresight CPU debug nodesSuzuki K Poulose2017-05-191-0/+24
| | | | | | | | | | | | | Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU debug areas are mapped at the same address for all revisions, like the ETM, even though the CPUs have changed from r1 to r2. Cc: Leo Yan <leo.yan@linaro.org> Cc: Mathieu Poirier <mathieu.porier@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [arranged nodes in ascending order with respect to register addresses] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add information about L1 and L2 cachesSudeep Holla2017-04-191-0/+42
| | | | | | | | | | | | | | | | | | Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a802431c527 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add missing CoreSight STM componentMike Leach2017-01-181-0/+16
| | | | | | | | | | | | | | | This patch adds the missing CoreSight STM component definition to the device tree of all the juno variants(r0,r1,r2) STM component is connected to different funnels depending on Juno platform variant. Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mike Leach <mike.leach@linaro.org> [sudeep.holla@arm.com: minor changelog update and reorganising the STM node back into juno-base.dtsi to avoid duplication] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: refactor CoreSight support on Juno r0Sudeep Holla2017-01-181-0/+8
| | | | | | | | | | | | | Currently the Coresight components are supported only on Juno r0 variant. In preparation to add support to Juno r1/r2 variants, this patch refactors the existing coresight device nodes so that r1/r2 support can be added easily. It also cleans up some of the device node names which were previously named so as they were confused as the labels rather than the node names. Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: remove dtsi nesting inside tree structureSudeep Holla2017-01-181-2/+1
| | | | | | | | | | | Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside the device tree structure. It's generally good practice to ensure that individual dtsi stand by themselves at the top of the file. This patch removes the nesting of the above mentioned dtsi files and makes them independent. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-12-151-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources: - Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time: - Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...
| * arm64: dts: juno: add cpu capacity-dmips-mhz information to R0 boardsJuri Lelli2016-10-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds cpu capacity-dmips-mhz information to Juno R0 boards. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <tixy@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | arm64: dts: juno: fix cluster sleep state entry latency on all SoC versionsSudeep Holla2016-12-021-1/+1
|/ | | | | | | | | | | | | | | | | The core and the cluster sleep state entry latencies can't be same as cluster sleep involves more work compared to core level e.g. shared cache maintenance. Experiments have shown on an average about 100us more latency for the cluster sleep state compared to the core level sleep. This patch fixes the entry latency for the cluster sleep state. Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree") Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: juno: add coresight supportSudeep Holla2016-06-211-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Most of the debug-related components on Juno are located in the coreSight subsystem while others are located in the Cortex-Axx clusters, the SCP subsystem, and in the main system. Each core in the two processor clusters contain an Embedded Trace Macrocell(ETM) which generates real-time trace information that trace tools can use and an ATB trace output that is sent to a funnel before going to the CoreSight subsystem. The trace output signals combine with two trace expansions using another funnel and fed into the Embedded Trace FIFO(ETF0). The output trace data stream of the funnel is then replicated before it is sent to either the: - Trace Port Interface Unit(TPIU), that sends it out using the trace port. - ETR that can write the trace data to memory located in the application memory space Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: Add idle-states to device treeJon Medhurst (Tixy)2015-12-221-0/+28
| | | | | | | | | | | This patch adds idle-states bindings data collected through a set of benchmarking experiments (latency and energy consumption) on Juno boards. Latencies data represents the worst case scenarios as required by the DT idle-states bindings. Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-11-101-0/+32
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
| * arm64: dts: add clock support for all the cpusSudeep Holla2015-10-091-0/+6
| | | | | | | | | | | | | | | | This patch adds the CPU clocks so that the CPU DVFS can be enabled. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
| * arm64: dts: add CPU topology on JunoSudeep Holla2015-10-091-0/+26
| | | | | | | | | | | | | | | | | | This patch adds CPU topology on Juno. It will be useful for ther other IP blocks depending on this topology. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
* | arm64: dts: juno: describe PMUs separatelyMark Rutland2015-10-071-7/+11
|/ | | | | | | | | | The A57 and A53 PMUs in Juno support different events, so describe them separately in both the Juno and Juno R1 DTs. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Juno: Split juno.dts into juno-base.dtsi and juno.dts.Liviu Dudau2015-05-221-128/+1
| | | | | | | | Prepare the device tree for adding more boards based on Juno r0. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Jon Medhurst <tixy@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: Juno: Fix the GIC node address label and the frequency of FAXI clock.Liviu Dudau2015-05-221-1/+1
| | | | | | | | | | | | | | | | During the review of the Juno DT files I've noticed that the GIC node label had two digits swapped leading to a different address being shown in the /sys/devices fs. Sudeep also pointed that public revisions of the Juno documentation list a different frequency for the FAXI system than what the one I've been using when creating the DT file. Verified with the firmware people to be the correct value in the shipped systems. Reported-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jon Medhurst <tixy@linaro.org>
* arm64: dts: add interrupt-affinity property to pmu node for junoWill Deacon2015-04-031-4/+10
| | | | | | | | | | | Make the Juno .dts robust against potential reordering of the CPU nodes by adding an explicit interrupt-affinity property to the PMU node. While we're at it, fix the PMU interrupts numbers too. Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm64: Add L2 cache topology to ARM Ltd boards/modelsSudeep Holla2015-02-251-0/+14
| | | | | | | | | | | | | | | | | Commit 5d425c18653731af6 ("arm64: kernel: add support for cpu cache information") adds cacheinfo support for ARM64. Since there's no architectural way of detecting the cpus that share particular cache, device tree can be used and the core cacheinfo already supports the same. This patch adds the L2 cache topology on Juno board, FVP/RTSM and foundation models. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: add baud rate to Juno stdout-pathRobin Murphy2015-01-231-1/+1
| | | | | | | | | | | Without explicit command-line parameters, the Juno UART ends up running at 57600 baud in the kernel, which is at odds with the 115200 baud used by the rest of the firmware. Since commit 7914a7c5651a5161 now lets us fix this by specifying default options in stdout-path, do so. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm64: ARM: Fix the Generic Timers interrupt active level descriptionLiviu Dudau2014-11-281-4/+4
| | | | | | | | | | | | The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional description" that generic timers provide an active-LOW interrupt output. Fix the device trees to correctly describe this. While doing this update the CPU mask to match the number of described CPUs as well. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: Add Juno board device tree.Liviu Dudau2014-11-201-0/+218
This adds support for ARM's Juno development board (rev 0). It enables most of the board peripherals: UART, I2C, USB, MMC and 100Mb ethernet. There is no support at the moment for clock setting and HDLCD driver which depends on it. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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