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* [ARM] Orion: PCIe x4/x1 detection supportLennert Buytenhek2008-06-221-0/+6
| | | | | | | | | | The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either be used in x4 mode or in quad x1 mode. This patch adds an accessor function to the generic plat-orion PCIe handling code to detect in which of the two modes we're running (which is determined by strap pins and/or configured by the bootloader). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR defineKe Wei2008-06-221-3/+3
| | | | | | | | | | | | Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: top-level IRQs are level-triggeredLennert Buytenhek2008-06-221-1/+2
| | | | | | | | | | | | | | | Make it clear that Orion top-level IRQs are level-triggered. This means that we don't need an ->ack() handler, or at least, we don't need the ->ack() handler (or the acking part of the ->mask_ack() handler) to actually do anything. Given that, we might as well point our ->mask_ack() handler at the ->mask() handler instead of providing a dummy ->ack() handler, since providing a ->mask_ack() handler on level IRQ sources will prevent ->ack() from ever being called. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] 4954/1: Orion: fix some function section mismatchNicolas Pitre2008-04-101-2/+2
| | | | | | | Without this, lspci won't work. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* plat-orion: share time handling codeLennert Buytenhek2008-03-272-1/+204
| | | | | | | | | Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* plat-orion: share PCIe handling codeLennert Buytenhek2008-03-272-1/+246
| | | | | | | | | Split off Orion PCIe handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* plat-orion: share IRQ handling codeLennert Buytenhek2008-03-272-1/+65
| | | | | | | | | | Split off Orion IRQ handling code into plat-orion/, and add support for multiple sets of (32) interrupts. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* plat-orion: introduceLennert Buytenhek2008-03-271-0/+8
Create arch/arm/plat-orion/, for peripherals shared between various Marvell Orion SoCs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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