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* mxc: changes to common plat-mxc code to add support for i.MX5Amit Kucheria2010-02-091-0/+13
| | | | | | | Prepare for i.MX5 SoC code by adding the relevant macros to common plat-mxc code. Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
* imx: define functions to configure chip selects in the WEIMUwe Kleine-König2010-01-081-0/+1
| | | | | | | | | | | | This has the addional effect that the macros CSCR_U, CSCR_L and CSCR_A are not used anymore in mach-pcm038.c and mach-qong.c. These still use the deprecated IO_ADDRESS macro and shouldn't be used in new code. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Dmitriy Taychenachev <dimichxp@gmail.com>
* imx: mangle addresses after adding the offsetUwe Kleine-König2010-01-081-3/+3
| | | | | | | | | | | | | | | | | | | | | don't use IO_ADDRESS($base) + $offset but IO_ADDRESS($base + $offset) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Rabin Vincent <rabin@rab.in> Cc: "Agustín Ferrín Pozuelo" <gatoguan-os@yahoo.com> Cc: Javier Martin <javier.martin@vista-silicon.com> Cc: Valentin Longchamp <valentin.longchamp@epfl.ch> Cc: Daniel Mack <daniel@caiaq.de> Cc: Dmitriy Taychenachev <dimichxp@gmail.com>
* MXC: add basic MXC91231 supportDmitriy Taychenachev2009-08-141-1/+14
| | | | | Signed-off-by: Dmitriy Taychenachev <dimichxp@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add i.MX25 supportSascha Hauer2009-08-141-0/+13
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* [ARM] MXC: add cpu_is_ macrosSascha Hauer2009-03-131-9/+65
| | | | | | | | | | We had hardcoded cpu_is_ macros for mxc architectures till now. As we want to run the same kernel on i.MX31 and i.MX35 this patch adds cpu_is_ macros which expand to 0 or 1 if only one architecture is compiled in and only check for the cpu type if more than one architecture is compiled in. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/imx2x: split i.MX21/i.MX27 register definitionsHolger Schurig2009-03-131-0/+4
| | | | | | | | | | | | * define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to CONFIG_ARCH_MX27, but this might change) * splits one header file. Memory definitions, interrupt sources, DMA channels are split into common part, i.MX27 specific and i.MX21 specific. * guard access to UART5/UART6, which don't exist on i.MX21 Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm/imx21: add kbuild support for the Freescale i.MX21Holger Schurig2009-03-131-0/+4
| | | | | | | | | | | | | * adds Kconfig variables * specifies different physical address for i.MX21 because of the different memory layouts * disables support for UART5/UART6 in the i.MX serial driver (the i.MX21 doesn't have those modules) Based on code from "Martin Fuzzey" <mfuzzey@gmail.com> Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mxc: add cscr register defintionsLuotao Fu2008-09-091-0/+6
| | | | | | | | | | This adds macros to get CSCR upper, lower and additional registers. These registers are needed to configure a chip select line. The offset layouts of these Registers are identical on mx27 and mx31, hence we can use the macros in generic way Signed-off-by: Luotao Fu <l.fu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-0/+36
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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