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* Merge branch 'for-next' of ↵Linus Torvalds2011-01-131-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (43 commits) Documentation/trace/events.txt: Remove obsolete sched_signal_send. writeback: fix global_dirty_limits comment runtime -> real-time ppc: fix comment typo singal -> signal drivers: fix comment typo diable -> disable. m68k: fix comment typo diable -> disable. wireless: comment typo fix diable -> disable. media: comment typo fix diable -> disable. remove doc for obsolete dynamic-printk kernel-parameter remove extraneous 'is' from Documentation/iostats.txt Fix spelling milisec -> ms in snd_ps3 module parameter description Fix spelling mistakes in comments Revert conflicting V4L changes i7core_edac: fix typos in comments mm/rmap.c: fix comment sound, ca0106: Fix assignment to 'channel'. hrtimer: fix a typo in comment init/Kconfig: fix typo anon_inodes: fix wrong function name in comment fix comment typos concerning "consistent" poll: fix a typo in comment ... Fix up trivial conflicts in: - drivers/net/wireless/iwlwifi/iwl-core.c (moved to iwl-legacy.c) - fs/ext4/ext4.h Also fix missed 'diabled' typo in drivers/net/bnx2x/bnx2x.h while at it.
| * Merge branch 'master' into for-nextJiri Kosina2010-12-226-29/+58
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS arch/arm/mach-omap2/pm24xx.c drivers/scsi/bfa/bfa_fcpim.c Needed to update to apply fixes for which the old branch was too outdated.
| * | ARM, mm: Don't include smp_plat.h twice in flush.cJesper Juhl2010-11-151-1/+0
| | | | | | | | | | | | | | | | | | | | | It's enough to include the asm/smp_plat.h once in arch/arm/mm/flush.c Signed-off-by: Jesper Juhl <jj@chaosbits.net> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | | Merge branch 'master' of ↵Paul Mundt2011-01-0717-264/+260
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into rmobile-latest Conflicts: arch/arm/mach-shmobile/Kconfig Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * \ \ Merge branch 'devel-stable' into develRussell King2011-01-061-1/+7
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
| | * | | ARM: mmp: select CPU_PJ4Haojian Zhuang2010-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2 configuration. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | ARM: pxa: support pxa95xHaojian Zhuang2010-12-181-0/+6
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | The core of PXA955 is PJ4. Add new PJ4 support. And add new macro CONFIG_PXA95x. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | Merge branch 'pgt' (early part) into develRussell King2011-01-0610-100/+128
| |\ \ \
| | * | | ARM: pgtable: provide RDONLY page table bit rather than WRITE bitRussell King2010-12-224-23/+22
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: invert L_PTE_EXEC to L_PTE_XNRussell King2010-12-223-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware page tables use an XN bit 'execute never'. Historically, we've had a Linux 'execute allow' bit, in the positive sense. Get rid of this artifact as future hardware will continue to have the XN sense. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: remove FIRST_USER_PGD_NRRussell King2010-12-221-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRST_USER_PGD_NR is now unnecessary, as this has been replaced by FIRST_USER_ADDRESS except in the architecture code. Fix up the last usage of FIRST_USER_PGD_NR, and remove the definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: use conventional page table code for identity mappingsRussell King2010-12-221-15/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove some knowledge of our 2-level page table layout from the identity mapping code - we assume that a step size of PGDIR_SIZE will allow us to step over all entries. While this is true today, it won't be true in the near future. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: collect up identity mapping functionsRussell King2010-12-223-37/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two places where we create identity mappings - one when we bring secondary CPUs online, and one where we setup some mappings for soft- reboot. Combine these two into a single implementation. Also collect the identity mapping deletion function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: switch order of Linux vs hardware page tablesRussell King2010-12-223-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This switches the ordering of the Linux vs hardware page tables in each page, thereby eliminating some of the arithmetic in the page table walks. As we now place the Linux page table at the beginning of the page, we can deal with the offset in the pgt by simply masking it away, along with the other control bits. This also makes the arithmetic all be positive, rather than a mixture. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: introduce pteval_t to represent a pte valueRussell King2010-11-263-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes everywhere dealing with pte values use the same type. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: use phys_addr_t for physical addressesRussell King2010-11-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that physical addresses are typed as phys_addr_t Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: use pXd_none_or_clear_bad() in pgd_free()Russell King2010-11-261-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove knowledge of the 2-level wrapping in pgd_free(), and use the pXd_none_or_clear_bad() macros when checking the entries. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: pgtable: get rid of get_pgd_slow()/free_pgd_slow()Russell King2010-11-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These old names are just aliases for pgd_alloc/pgd_free. Just use the new names. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge branch 'misc' into develRussell King2011-01-066-16/+77
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
| | * \ \ \ Merge branch 'smp' into miscRussell King2011-01-061-1/+1
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/kernel/entry-armv.S arch/arm/mm/ioremap.c
| | * | | | | ARM: DMA: add support for DMA debuggingRussell King2011-01-061-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ARM support for the DMA debug infrastructure, which allows the DMA API usage to be debugged. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()Russell King2011-01-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the page_to_dma() and dma_to_page() macros with their PFN equivalents. This allows us to map parts of memory which do not have a struct page allocated to them to bus addresses. This will be used internally by dma_alloc_coherent()/dma_alloc_writecombine(). Build tested on Versatile, OMAP1, IOP13xx and KS8695. Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | Revert "ARM: relax ioremap prohibition (309caa9) for -final and -stable"Russell King2010-12-241-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 06c1088, as promised in the warning message.
| | * | | | | ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processorsLeif Lindholm2010-11-042-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when user RO. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUsCatalin Marinas2010-11-044-5/+21
| | | |_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: fix cache-feroceon-l2 after stack based kmap_atomic()Nicolas Pitre2010-12-191-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3e4d3af501 "mm: stack based kmap_atomic()", it is actively wrong to rely on fixed kmap type indices (namely KM_L2_CACHE) as kmap_atomic() totally ignores them and a concurrent instance of it may happily reuse any slot for any purpose. Because kmap_atomic() is now able to deal with reentrancy, we can get rid of the ad hoc mapping here. While the code is made much simpler, there is a needless cache flush introduced by the usage of __kunmap_atomic(). It is not clear if the performance difference to remove that is worth the cost in code maintenance (I don't think there are that many highmem users on that platform anyway) but that should be reconsidered when/if someone cares enough to do some measurements. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * | | | | ARM: fix cache-xsc3l2 after stack based kmap_atomic()Nicolas Pitre2010-12-191-36/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3e4d3af501 "mm: stack based kmap_atomic()", it is actively wrong to rely on fixed kmap type indices (namely KM_L2_CACHE) as kmap_atomic() totally ignores them and a concurrent instance of it may happily reuse any slot for any purpose. Because kmap_atomic() is now able to deal with reentrancy, we can get rid of the ad hoc mapping here, and we even don't have to disable IRQs anymore (highmem case). While the code is made much simpler, there is a needless cache flush introduced by the usage of __kunmap_atomic(). It is not clear if the performance difference to remove that is worth the cost in code maintenance (I don't think there are that many highmem users on that platform if at all anyway). Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * | | | | ARM: get rid of kmap_high_l1_vipt()Nicolas Pitre2010-12-193-93/+8
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3e4d3af501 "mm: stack based kmap_atomic()", it is no longer necessary to carry an ad hoc version of kmap_atomic() added in commit 7e5a69e83b "ARM: 6007/1: fix highmem with VIPT cache and DMA" to cope with reentrancy. In fact, it is now actively wrong to rely on fixed kmap type indices (namely KM_L1_CACHE) as kmap_atomic() totally ignores them now and a concurrent instance of it may reuse any slot for any purpose. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* | | | | Merge branch 'rmobile/urgent' into rmobile-latestPaul Mundt2010-12-214-26/+55
|\ \ \ \ \ | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-shmobile/include/mach/entry-macro.S Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | ARM: 6535/1: V6 MPCore v6_dma_inv_range and v6_dma_flush_range RWFO fixValentine Barshak2010-12-141-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache ownership must be acquired by reading/writing data from the cache line to make cache operation have the desired effect on the SMP MPCore CPU. However, the ownership is never acquired in the v6_dma_inv_range function when cleaning the first line and flushing the last one, in case the address is not aligned to D_CACHE_LINE_SIZE boundary. Fix this by reading/writing data if needed, before performing cache operations. While at it, fix v6_dma_flush_range to prevent RWFO outside the buffer. Cc: stable@kernel.org Signed-off-by: Valentine Barshak <vbarshak@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6528/1: Use CTR for the I-cache line size on ARMv7Catalin Marinas2010-12-122-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7Catalin Marinas2010-12-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of the dcache_line_size macro reads the L1 cache size from the CCSIDR register. This, however, is not guaranteed to be the smallest cache line in the cache hierarchy. The patch changes to the macro to use the more architecturally correct CTR register. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in ↵Dave Martin2010-11-301-2/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mm/proc-v7.S Directives such as .long and .word do not magically cause the assembler location counter to become aligned in gas. As a result, using these directives in code sections can result in misaligned data words when building a Thumb-2 kernel (CONFIG_THUMB2_KERNEL). This is a Bad Thing, since the ABI permits the compiler to assume that fundamental types of word size or above are word- aligned when accessing them from C. If the data is not really word-aligned, this can cause impaired performance and stray alignment faults in some circumstances. In general, the following rules should be applied when using data word declaration directives inside code sections: * .quad and .double: .align 3 * .long, .word, .single, .float: .align (or .align 2) * .short: No explicit alignment required, since Thumb-2 instructions are always 2 or 4 bytes in size. immediately after an instruction. In this specific case, we can achieve the desired alignment by forcing a 32-bit branch instruction using the W() macro, since the assembler location counter is already 32-bit aligned in this case. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | Merge branch 'rmobile/mmcif' into rmobile-latestPaul Mundt2010-11-251-2/+2
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| * | | ARM: avoid annoying <4>'s in printk outputRussell King2010-11-231-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | Adding KERN_WARNING in the middle of strings now produces those tokens in the output, rather than accepting the level as was once the case. Fix this in the one reported case. There might be more... Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: mach-shmobile: Initial AG5 and AG5EVM supportMagnus Damm2010-11-181-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | ARM: Fix DMA coherent allocator alignmentRussell King2010-11-071-1/+1
|/ | | | | | | | | An out by one bug meant that the DMA coherent allocator was aligning to one more bit than it should, causing it to run out of available memory quicker. Fix this. Reported-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-10-3023-89/+478
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (215 commits) ARM: memblock: setup lowmem mappings using memblock ARM: memblock: move meminfo into find_limits directly ARM: memblock: convert free_highpages() to use memblock ARM: move freeing of highmem pages out of mem_init() ARM: memblock: convert memory detail printing to use memblock ARM: memblock: use memblock to free memory into arm_bootmem_init() ARM: memblock: use memblock when initializing memory allocators ARM: ensure membank array is always sorted ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ARM: 6464/2: fix spinlock recursion in adjust_pte() ARM: fix memblock breakage ARM: 6465/1: Fix data abort accessing proc_info from __lookup_processor_type ARM: 6460/1: ixp2000: fix type of ixp2000_timer_interrupt ARM: 6449/1: Fix for compiler warning of uninitialized variable. ARM: 6445/1: fixup TCM memory types ARM: imx: Add wake functionality to GPIO ARM: mx5: Add gpio-keys to mx51 babbage board ARM: imx: Add gpio-keys to plat-mxc mx31_3ds: Fix spi registration mx31_3ds: Fix the logic for detecting the debug board ...
| * Merge branch 'devel-stable' into develRussell King2010-10-282-6/+80
| |\
| | * Merge branch 'l2x0-pull-rmk' of ↵Russell King2010-10-282-6/+80
| | |\ | | | | | | | | | | | | git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
| | | * ARM: l2x0: Optimise the range based operationsSantosh Shilimkar2010-10-261-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the big buffers which are in excess of cache size, the maintaince operations by PA are very slow. For such buffers the maintainace operations can be speeded up by using the WAY based method. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| | | * ARM: l2x0: Determine the cache sizeSantosh Shilimkar2010-10-261-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache size is needed for to optimise range based maintainance operations Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| | | * arm: Implement l2x0 cache disable functionsThomas Gleixner2010-10-261-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add flush_all, inv_all and disable functions to the l2x0 code. These functions are called from kexec code to prevent random crashes in the new kernel. Platforms like OMAP which control L2 enable/disable via SMI mode can override the outer_cache.disable() function to implement their own. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| | | * ARM: Improve the L2 cache performance when PL310 is usedCatalin Marinas2010-10-262-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this L2 cache controller, the cache maintenance by PA and sync operations are atomic and do not require a "wait" loop. This patch conditionally defines the cache_wait() function. Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch automatically enables CACHE_PL310 when only CPU_V7 is defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | ARM: memblock: setup lowmem mappings using memblockRussell King2010-10-281-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use memblock information to setup lowmem mappings rather than the membank array. This allows platforms to manipulate the memblock information during initialization to reserve (and remove) memory from the kernel's view of memory - and thus allowing platforms to setup their own private mappings for this memory without causing problems with multiple aliasing mappings: size = min(size, SZ_2M); base = memblock_alloc(size, min(align, SZ_2M)); memblock_free(base, size); memblock_remove(base, size); This is needed because multiple mappings of regions with differing attributes (sharability, type, cache) are not permitted with ARMv6 and above. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: memblock: move meminfo into find_limits directlyRussell King2010-10-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bootmem_init() no longer makes several uses of the membank information, so move this into the one remaining called function which does use it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: memblock: convert free_highpages() to use memblockRussell King2010-10-281-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Free the high pages using the memblock memory lists - and more importantly, exclude any memblock allocations in highmem from the free'd memory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: move freeing of highmem pages out of mem_init()Russell King2010-10-281-10/+17
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: memblock: convert memory detail printing to use memblockRussell King2010-10-281-3/+6
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: memblock: use memblock to free memory into arm_bootmem_init()Russell King2010-10-281-17/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch arm_bootmem_init() to use memblock instead of membank to free memory into bootmem. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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