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* ARM: 6144/1: TCM memory bug freeing bugLinus Walleij2010-05-271-3/+3
| | | | | | | | | | | | This fixes a bug in mm/init.c when freeing the TCM compile memory, this was being referred to as a char * which is incorrect: this will dereference the pointer and feed in the value at the location instead of the address to it. Change it to a plain char and use &(char) to reference it. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MPSantosh Shilimkar2010-05-201-0/+4
| | | | | | | | | | This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linuxLinus Torvalds2010-05-191-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux: (98 commits) Input: s3c24xx_ts - depend on SAMSUNG_DEV_TS and update menu entry Input: s3c24xx_ts - Add FEAT for Samsung touchscreen support Input: s3c24xx_ts - Implement generic GPIO configuration callback ARM: SAMSUNG: Move s3c64xx dev-ts.c to plat-samsung and rename configuration ARM: SAMSUNG: Implements cfg_gpio function for Samsung touchscreen ARM: S3C64XX: Add touchscreen platform device definition ARM: SAMSUNG: Move mach/ts.h to plat/ts.h ARM: S5PC100: Move i2c helpers from plat-s5pc1xx to mach-s5pc100 ARM: S5PC100: Move frame buffer helpers from plat-s5pc1xx to mach-s5pc100 ARM: S5PC100: gpio.h cleanup ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100 ARM: S5PC100: Use common functions for gpiolib implementation drivers: serial: S5PC100 serial driver cleanup ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move ARM: SAMSUNG: Copy common I2C0 device helpers to machine directories ARM: SAMSUNG: move driver strength gpio configuration helper to common dir ARM: S5PV210: Add GPIOlib support ARM: SAMSUNGy: fix broken timer irq base ARM: SMDK6440: Add audio devices on board ARM: S5P6440: Add audio platform devices ...
| * ARM: RX1950: Add suspend/resume support for RX1950Vasily Khoruzhick2010-05-121-2/+3
| | | | | | | | | | Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-05-1910-75/+149
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (224 commits) ARM: remove 'select GENERIC_TIME' ARM: 6136/1: ARCH_REQUIRE_GPIOLIB selects GENERIC_GPIO ARM: 6074/1: oprofile: convert from sysdev to platform device ARM: 6073/1: oprofile: remove old files and update KConfig ARM: 6072/1: oprofile: use perf-events framework as backend ARM: 6071/1: perf-events: allow modules to query the number of hardware counters ARM: 6070/1: perf-events: add support for xscale PMUs ARM: 6069/1: perf-events: use numeric ID to identify PMU ARM: 6064/1: pmu: register IRQs at runtime ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMA ARM: 6134/1: Handle instruction cache maintenance fault properly ARM: nwfpe: allow debugging output to be configured at runtime ARM: rename mach_cpu_disable() to platform_cpu_disable() ARM: 6132/1: PL330: Add common core driver ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310 ARM: Move memory mapping into mmu.c ARM: Ensure meminfo is sorted prior to sanity_check_meminfo ARM: Remove useless linux/bootmem.h includes ARM: convert /proc/cpu/aligment to seq_file arm: use asm-generic/scatterlist.h ...
| * \ Merge branch 'devel-stable' into develRussell King2010-05-1714-49/+186
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/include/asm/system.h arch/arm/mm/Kconfig
| | * \ Merge branch 'devel' of ↵Russell King2010-05-132-11/+5
| | |\ \ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
| | | * | [ARM] mmp: enable L2 in mmp2Haojian Zhuang2010-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | Merge branch 'gemini_fix' of git://git.berlios.de/gemini-board into devel-stableRussell King2010-05-071-1/+1
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| | | * | | ARM: Gemini: fix compiler error in copypage-fa.cHans Ulli Kroll2010-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix compiler error in copypage-fs.c missing struct vm_area_struct *vma in function fa_copy_user_highpage Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
| | * | | | arm: mm: qsd8x50: Fix incorrect permission faultsDave Estes2010-05-032-0/+23
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle incorrectly reported permission faults for qsd8650. On permission faults, retry MVA to PA conversion. If retry detects translation fault. Report as translation fault. Cc: Jamie Lokier <jamie@shareable.org> Signed-off-by: Dave Estes <cestes@quicinc.com>
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| *---. \ \ \ Merge branches 'at91', 'bcmring', 'ep93xx', 'iop', 'misc', 'nomadik', ↵Russell King2010-05-178-73/+124
| |\ \ \ \ \ \ | | |_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'omap', 'pxa', 'spear' and 'versatile' into devel Conflicts: arch/arm/Makefile arch/arm/common/Makefile arch/arm/mm/Kconfig
| | | | * | | ARM: Add Versatile Express CA9x4 processor supportRussell King2010-05-021-1/+2
| | |_|/ / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: 6027/1: ux500: enable l2x0 supportSrinidhi Kasagar2010-04-141-1/+2
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the l2x0 support and ensures that the secondary CPU can see the page table and secondary data at this point. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMARussell King2010-05-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a configuration option to allow the ARMv6 to use normal bufferable memory for coherent DMA. This option is forced to 'y' for ARMv7, and offered as a configuration option on ARMv6. Enabling this option requires drivers to have the necessary barriers to ensure that data in DMA coherent memory is visible prior to the DMA operation commencing. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6134/1: Handle instruction cache maintenance fault properlyKirill A. Shutemov2010-05-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Between "clean D line..." and "invalidate I line" operations in v7_coherent_user_range(), the memory page may get swapped out. And the fault on "invalidate I line" could not be properly handled causing the oops. In ARMv6 "external abort on linefetch" replaced by "instruction cache maintenance fault". Let's handle it as translation fault. It fixes the issue. I'm not sure if it's reasonable to check arch version in run-time. Let's do it in compile time for now. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan2010-05-151-5/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L310 cache controller's interface is almost identical to the L210. One major difference is that the PL310 can have up to 16 ways. This change uses the cache's part ID and the Associativity bits in the AUX_CTRL register to determine the number of ways. Also, this version prints out the CACHE_ID and AUX_CTRL registers. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: Move memory mapping into mmu.cRussell King2010-05-153-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: Ensure meminfo is sorted prior to sanity_check_meminfoRussell King2010-05-152-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: convert /proc/cpu/aligment to seq_fileAlexey Dobriyan2010-05-151-27/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert code away from ->read_proc/->write_proc interfaces. Switch to proc_create()/proc_create_data() which makes addition of proc entries reliable wrt NULL ->proc_fops, NULL ->data and so on. Problem with ->read_proc et al is described here commit 786d7e1612f0b0adb6046f19b906609e4fe8b1ba "Fix rmmod/read/write races in /proc entries" This patch is part of an effort to remove the old simple procfs PAGE_SIZE buffer interface. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: remove unnecessary cache flushRussell King2010-04-141-2/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cache flush occurs when we first insert a page into the page tables, where a page did not exist previously. There can be no cache lines associated with this virtual mapping, so this cache flush is redundant. Tested-by: Mike Rapoport <mike@compulab.co.il> Tested-by: Mikael Pettersson <mikpe at it.uu.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas2010-05-082-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache opsCatalin Marinas2010-05-081-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Snoop Control Unit on the ARM11MPCore hardware does not detect the cache operations and the dma_cache_maint*() functions may leave stale cache entries on other CPUs. The solution implemented in this patch performs a Read or Write For Ownership in the ARMv6 DMA cache maintenance functions. These LDR/STR instructions change the cache line state to shared or exclusive so that the cache maintenance operation has the desired effect. Tested-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6106/1: Implement copy_to_user_page() for noMMUCatalin Marinas2010-05-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7959722 introduced calls to copy_(to|from)_user_page() from access_process_vm() in mm/nommu.c. The copy_to_user_page() was not implemented on noMMU ARM. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.cCatalin Marinas2010-05-081-2/+2
| |_|/ |/| | | | | | | | | | | | | | | | | | | | Commit 31aa8fd6 introduced the __arm_ioremap_caller() function but the nommu.c version did not have the _caller suffix. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: 6093/1: Fix kernel memory printing for sparsememCatalin Marinas2010-05-041-10/+4
| |/ |/| | | | | | | | | | | | | | | | | | | The show_mem() and mem_init() function are assuming that the page map is contiguous and calculates the start and end page of a bank using (map + pfn). This fails with SPARSEMEM where pfn_to_page() must be used. Tested-by: Will Deacon <Will.Deacon@arm.com> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: fix build error in arch/arm/kernel/process.cRussell King2010-04-212-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /tmp/ccJ3ssZW.s: Assembler messages: /tmp/ccJ3ssZW.s:1952: Error: can't resolve `.text' {.text section} - `.LFB1077' This is caused because: .section .data .section .text .section .text .previous does not return us to the .text section, but the .data section; this makes use of .previous dangerous if the ordering of previous sections is not known. Fix up the other users of .previous; .pushsection and .popsection are a safer pairing to use than .section and .previous. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6052/1: kdump: make kexec work in interrupt contextMika Westerberg2010-04-141-4/+6
| | | | | | | | | | | | | | | | When crash happens in interrupt context there is no userspace context. We always use current->active_mm in those cases. Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6007/1: fix highmem with VIPT cache and DMANicolas Pitre2010-04-144-19/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VIVT cache of a highmem page is always flushed before the page is unmapped. This cache flush is explicit through flush_cache_kmaps() in flush_all_zero_pkmaps(), or through __cpuc_flush_dcache_area() in kunmap_atomic(). There is also an implicit flush of those highmem pages that were part of a process that just terminated making those pages free as the whole VIVT cache has to be flushed on every task switch. Hence unmapped highmem pages need no cache maintenance in that case. However unmapped pages may still be cached with a VIPT cache because the cache is tagged with physical addresses. There is no need for a whole cache flush during task switching for that reason, and despite the explicit cache flushes in flush_all_zero_pkmaps() and kunmap_atomic(), some highmem pages that were mapped in user space end up still cached even when they become unmapped. So, we do have to perform cache maintenance on those unmapped highmem pages in the context of DMA when using a VIPT cache. Unfortunately, it is not possible to perform that cache maintenance using physical addresses as all the L1 cache maintenance coprocessor functions accept virtual addresses only. Therefore we have no choice but to set up a temporary virtual mapping for that purpose. And of course the explicit cache flushing when unmapping a highmem page on a system with a VIPT cache now can go, which should increase performance. While at it, because the code in __flush_dcache_page() has to be modified anyway, let's also make sure the mapped highmem pages are pinned with kmap_high_get() for the duration of the cache maintenance operation. Because kunmap() does unmap highmem pages lazily, it was reported by Gary King <GKing@nvidia.com> that those pages ended up being unmapped during cache maintenance on SMP causing segmentation faults. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: Fix ioremap_cached()/ioremap_wc() for SMP platformsRussell King2010-04-091-0/+4
| | | | | | | | | | | | | | | | | | Write combining/cached device mappings are not setting the shared bit, which could potentially cause problems on SMP systems since the cache lines won't participate in the cache coherency protocol. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | Merge branch 'master' into export-slabhTejun Heo2010-04-052-0/+23
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| * | ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4)Catalin Marinas2010-03-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor systems for things like ordering Normal Non-cacheable memory accesses with DMA transfer (via Device memory writes). The current implementation uses dmb() for mb() and friends but this is not sufficient. The DMB only ensures the relative ordering of the observability of accesses by other processors or devices acting as masters. In case of DMA transfers started by writes to device memory, the relative ordering is not ensured because accesses to slave ports of a device are not considered observable by the DMB definition. A DSB is required for the data to reach the main memory (even if mapped as Normal Non-cacheable) before the device receives the notification to begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or PL310) buffer stores to Normal Non-cacheable memory and this would need to be drained with the outer_sync() function call. The patch also allows platforms to define their own mandatory barriers implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a mach/barriers.h file. Note that the SMP barriers are unchanged (being DMBs as before) since they are only guaranteed to work with Normal Cacheable memory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)Catalin Marinas2010-03-252-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4)Catalin Marinas2010-03-251-0/+6
| |/ | | | | | | | | | | | | | | | | This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo2010-03-304-1/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-03-0141-361/+1143
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits) ARM: Eliminate decompressor -Dstatic= PIC hack ARM: 5958/1: ARM: U300: fix inverted clk round rate ARM: 5956/1: misplaced parentheses ARM: 5955/1: ep93xx: move timer defines into core.c and document ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c ARM: 5953/1: ep93xx: fix broken build of clock.c ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig ARM: 5949/1: NUC900 add gpio virtual memory map ARM: 5948/1: Enable timer0 to time4 clock support for nuc910 ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk ARM: make_coherent(): fix problems with highpte, part 2 MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself ARM: 5945/1: ep93xx: include correct irq.h in core.c ARM: 5933/1: amba-pl011: support hardware flow control ARM: 5930/1: Add PKMAP area description to memory.txt. ARM: 5929/1: Add checks to detect overlap of memory regions. ARM: 5928/1: Change type of VMALLOC_END to unsigned long. ARM: 5927/1: Make delimiters of DMA area globally visibly. ARM: 5926/1: Add "Virtual kernel memory..." printout. ARM: 5920/1: OMAP4: Enable L2 Cache ... Fix up trivial conflict in arch/arm/mach-mx25/clock.c
| * Merge branches 'clks' and 'pnx' into develRussell King2010-02-253-5/+10
| |\
| * \ Merge branch 'misc2' into develRussell King2010-02-259-93/+343
| |\ \
| | * | ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH ↵Kukjin Kim2010-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: Ben Dooks <ben-linux@fluff.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5929/1: Add checks to detect overlap of memory regions.Fenkart/Bostandzhyan2010-02-151-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5928/1: Change type of VMALLOC_END to unsigned long.Fenkart/Bostandzhyan2010-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes it consistent with VMALLOC_START Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5927/1: Make delimiters of DMA area globally visibly.Fenkart/Bostandzhyan2010-02-152-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds DMA area to 'virtual memory map' startup message Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5926/1: Add "Virtual kernel memory..." printout.Fenkart/Bostandzhyan2010-02-151-9/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code based on parisc and x86_32. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate ↵Santosh Shilimkar2010-02-151-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clean lines This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5917/1: OMAP4: Add L2 Cache supportSantosh Shilimkar2010-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar2010-02-151-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the cache maintainance by line helper functions. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selectedTony Lindgren2010-02-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas2010-02-151-14/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ASID allocation algorithm doesn't ensure the notification of the other CPUs when the ASID rolls over. This may lead to two processes using the same ASID (but different generation) or multiple threads of the same process using different ASIDs. This patch adds the broadcasting of the ASID rollover event to the other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid" during the handling of the broadcast, the ASID numbering now starts at "smp_processor_id() + 1". At rollover, the cpu_last_asid will be set to NR_CPUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 5880/1: arm: use generic infrastructure for early paramsJeremy Kerr2010-02-152-25/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM setup code includes its own parser for early params, there's also one in the generic init code. This patch removes __early_init (and related code) from arch/arm/kernel/setup.c, and changes users to the generic early_init macro instead. The generic macro takes a char * argument, rather than char **, so we need to update the parser functions a little. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: Move creation of /proc/cpu out of alignment.cRussell King2010-02-151-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Always creating this directory avoids other users having to jump through silly hoops when they want to share this directory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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