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* [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-241-1/+1
| | | | | | | | | | The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Add a prefetch abort handlerPaul Brook2008-04-181-0/+1
| | | | | | | | | This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] 4864/1: Enable write buffer coalescing on IOPArnaud Patard2008-03-201-0/+4
| | | | | | | | Some bootloaders are disabling write buffer coalescing. Enable it back under linux. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4311/1: ixp4xx: add KIXRP435 platformRuslan V. Sushko2007-04-211-0/+28
| | | | | | | | | | Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4100/1: iop3xx: fix cpu mask for iop333Dan Williams2007-01-241-1/+1
| | | | | | | | cosmetic fix so iop333 is not reported as ixp46x iop333 cpuid = 0x69054210 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Unuse another Linux PTE bitRussell King2006-12-131-3/+3
| | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3881/4: xscale: clean up cp0/cp1 handlingLennert Buytenhek2006-12-031-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Include asm/elf.h instead of asm/procinfo.hRussell King2006-11-301-1/+1
| | | | | | | These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3912/1: Make PXA270 advertise HWCAP_IWMMXT capabilityPaul Gortmaker2006-11-021-1/+1
| | | | | | | | | | | | | ARM patch 3756/1 added HWCAP_IWMMXT. This patch adds support for broadcasting that info via /proc/cpuinfo and sets it for the CPU features of the PXA270. I've booted 19rc3 on a pxa270 and confirmed that the /proc/cpuinfo shows "iwmmxt" in the Features. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3814/1: move 80200 dma_inv_range() erratum check out of lineLennert Buytenhek2006-09-251-6/+52
| | | | | | | | | | | | | | | On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't clear the dirty bits, which means that if we invalidate a dirty line, the dirty data can still be written back to memory later on. To work around this, dma_inv_range() on these two processors is implemented as dma_flush_range() (i.e. do a clean D-cache line before doing the invalidate D-cache line.) For this, we currently have a processor ID check in xscale_dma_inv_range(), but a better solution is to add a separate cache_fns and proc_info for A0/A1 80200. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3780/1: Fix iop321 cpuidDan Williams2006-09-141-1/+1
| | | | | | | | | Patch from Dan Williams commit a6a38a66224c7c578cfed2f584b440c81af0c3ae changed the iop321 id to a value that does not work with all platforms. Change the mask to permit bit 11. Tested on an iq80321 600Mhz CRB. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32xLennert Buytenhek2006-07-291-1/+29
| | | | | | | | | | | | | | | Patch from Lennert Buytenhek The IOP 80219 xscale CPU is a stripped down version of the IOP32x. But the fact that the 80219 and IOP32x are very similar doesn't mean that they need to share a cpu table entry. It's also somewhat confusing for the end user to see the 80219 reported as an IOP32x, so this patch splits the IOP32x cpu table entry to make a separate entry for the 80219. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3541/2: workaround for PXA27x erratum E7Nicolas Pitre2006-07-011-1/+7
| | | | | | | | | | | | | | | Patch from Nicolas Pitre According to the Intel PXA27x Processor Family Specification Update document (doc.nr. 280071-009) erratum E7, some care must be taken to locate the disabling and re-enabling of the MMU to the beginning of a cache line to avoid problems in some circumstances. Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this up. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu branchRussell King2006-07-011-9/+7
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| * [ARM] nommu: provide a way for correct control register value selectionRussell King2006-06-291-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Set bit 4 on section mappings correctly depending on CPURussell King2006-06-291-1/+38
|/ | | | | | | | | | | | | | On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu treeRussell King2006-03-251-0/+1
|\ | | | | | | | | | | Fix merge conflict in arch/arm/mm/proc-xscale.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.hRussell King2006-03-211-0/+1
| | | | | | | | | | | | | | Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Remove unnecessary asm/hardware.h includesRussell King2006-03-211-1/+0
|/ | | | | | | | | asm/hardware.h is not required for the majority of processor support files, ioremap support, mm initialisation, acorn IO support, nor the debug code (which picks up its machine specific includes via debug-macros.S) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_rangeNicolas Pitre2006-02-011-5/+11
| | | | | | | | | | Patch from Nicolas Pitre The mini I-cache issue is valid only for kernel space since debuggers would not fly if they used user space addresses for their stubs. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck`Ben Dooks2005-09-201-1/+1
| | | | | | | | | | | Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2839/1: Remove XScale cache and TLB locking codeDeepak Saxena2005-08-031-136/+0
| | | | | | | | | | | Patch from Deepak Saxena The XScale locking code is not something that has been validated on 2.6 and needs to be replaced with a more generic API to use with other ARMs that support locking features. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+934
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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