summaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-macros.S
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'devel-stable' into develRussell King2009-09-121-0/+2
|\ | | | | | | | | | | Conflicts: MAINTAINERS arch/arm/mm/fault.c
| * nommu: Add #ifdef CONFIG_MMU around the PTE sanity checksCatalin Marinas2009-07-241-0/+2
| | | | | | | | Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | [ARM] remove L_PTE_BUFFERABLE and L_PTE_CACHEABLERussell King2009-07-111-6/+0
|/ | | | | | | | These old symbols are meaningless now that we have memory type support implemented. The entire memory type field needs to be modified rather than just a few bits twiddled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-011-1/+1
| | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-011-2/+28
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-011-0/+144
| | | | | | | There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] armv7: add support for ARMv7 cores.Catalin Marinas2007-05-081-0/+12
| | | | | | | This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: provide a way for correct control register value selectionRussell King2006-06-291-0/+10
| | | | | | | | | | | | | | | | | | Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* kbuild: arm - use generic asm-offsets.h supportSam Ravnborg2005-09-091-1/+1
| | | | | | | Delete obsoleted stuff from arch Makefile and rename constants.h to asm-offsets.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+51
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
OpenPOWER on IntegriCloud