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* ARM: tegra: Rename tegra20 clock filePrashant Gaikwad2012-09-061-1458/+0
| | | | | | | | Make the name consistent with other files. s/tegra2/tegra20 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra20: Separate out clk ops and clk dataPrashant Gaikwad2012-09-061-1042/+16
| | | | | | | | | Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix U16 divider range checkStephen Warren2012-09-061-1/+1
| | | | | | | | | | | | | | | | | A U16 divider can divide a clock by 1..64K. However, the range-check in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check. In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Provide clock for only one PWM controllerThierry Reding2012-07-021-5/+1
| | | | | | | | | A subsequent patch will add a generic PWM API driver for the Tegra PWFM controller, supporting all four PWM devices with a single PWM chip. The device will be named tegra-pwm and only one clock needs to be provided. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Fix PWM clock programmingSimon Que2012-07-021-4/+28
| | | | | | | | | | | | | | | | PWM clock source registers in Tegra 2 have different clock source selection bit fields than other registers. PWM clock source bits in CLK_SOURCE_PWM_0 register are located at bit field bit[30:28] while others are at bit field bit[31:30] in their respective clock source register. This patch updates the clock programming to correctly reflect that, by adding a flag to indicate the alternate bit field format and checking for it when selecting a clock source (parent clock). Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Simon Que <sque@chromium.org> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"Laxman Dewangan2012-06-261-1/+1
| | | | | | | | | | | Rename the driver name of the clock entry of Tegra APBDMA to tegra-apbdma from of tegra-dma. This name is more aligned towards the movement of dmaengine based new DMA driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Remove second instance of uart clkPrashant Gaikwad2012-06-251-10/+10
| | | | | | | | | | In Tegra30 clock file two clk objects were created for same UART clock. Remove the duplicates and add clock aliases instead. Update the Tegra20 clock file to make the names consistent. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-05-261-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm-soc driver specific updates from Olof Johansson: "These changes are specific to some driver that may be used by multiple boards or socs. The most significant change in here is the move of the samsung iommu code from a platform specific in-kernel interface to the generic iommu subsystem." Fix up trivial conflicts in arch/arm/mach-exynos/Kconfig * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits) mmc: dt: Consolidate DT bindings iommu/exynos: Add iommu driver for EXYNOS Platforms ARM: davinci: optimize the DMA ISR ARM: davinci: implement DEBUG_LL port choice ARM: tegra: Add SMMU enabler in AHB ARM: tegra: Add Tegra AHB driver Input: pxa27x_keypad add choice to set direct_key_mask Input: pxa27x_keypad direct key may be low active Input: pxa27x_keypad bug fix for direct_key_mask Input: pxa27x_keypad keep clock on as wakeup source ARM: dt: tegra: pinmux changes for USB ULPI ARM: tegra: add USB ULPI PHY reset GPIO to device tree ARM: tegra: don't hard-code USB ULPI PHY reset_gpio ARM: tegra: change pll_p_out4's rate to 24MHz ARM: tegra: fix pclk rate ARM: tegra: reparent sclk to pll_c_out1 ARM: tegra: Add pllc clock init table ARM: dt: tegra cardhu: basic audio support ARM: dt: tegra30.dtsi: Add audio-related nodes ARM: tegra: add AUXDATA required for audio ...
| * ARM: tegra: Add pllc clock init tableAllen Martin2012-04-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[] so that it's possible to explicitly initialize the PLL. NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output, whereas the ChromeOS kernel contains entries for 600MHz output. I chose to upstream the ChromeOS values for now, since the 600MHz rate appears to match the default rate of this PLL when the HW boots, and it's not clear to me why 522 or 598MHz are more useful. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Olof Johansson <olofj@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> [swarren: wrote commit description]
* | Merge tag 'sound-3.5' of ↵Linus Torvalds2012-05-231-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "This is the first big chunk for 3.5 merges of sound stuff. There are a few big changes in different areas. First off, the streaming logic of USB-audio endpoints has been largely rewritten for the better support of "implicit feedback". If anything about USB got broken, this change has to be checked. For HD-audio, the resume procedure was changed; instead of delaying the resume of the hardware until the first use, now waking up immediately at resume. This is for buggy BIOS. For ASoC, dynamic PCM support and the improved support for digital links between off-SoC devices are major framework changes. Some highlights are below: * HD-audio - Avoid accesses of invalid pin-control bits that may stall the codec - V-ref setup cleanups - Fix the races in power-saving code - Fix the races in codec cache hashes and connection lists - Split some common codes for BIOS auto-parser to hda_auto_parser.c - Changed the PM resume code to wake up immediately for buggy BIOS - Creative SoundCore3D support - Add Conexant CX20751/2/3/4 codec support * ASoC - Dynamic PCM support, allowing support for SoCs with internal routing through components with tight sequencing and formatting constraints within their internal paths or where there are multiple components connected with CPU managed DMA controllers inside the SoC. - Greatly improved support for direct digital links between off-SoC devices, providing a much simpler way of connecting things like digital basebands to CODECs. - Much more fine grained and robust locking, cleaning up some of the confusion that crept in with multi-component. - CPU support for nVidia Tegra 30 I2S and audio hub controllers and ST-Ericsson MSP I2S controolers - New CODEC drivers for Cirrus CS42L52, LAPIS Semiconductor ML26124, Texas Instruments LM49453. - Some regmap changes needed by the Tegra I2S driver. - mc13783 audio support. * Misc - Rewrite with module_pci_driver() - Xonar DGX support for snd-oxygen - Improvement of packet handling in snd-firewire driver - New USB-endpoint streaming logic - Enhanced M-audio FTU quirks and relevant cleanups - Increment the support of OSS devices to 256 - snd-aloop accuracy improvement There are a few more pending changes for 3.5, but they will be sent slightly later as partly depending on the changes of DRM." Fix up conflicts in regmap (due to duplicate patches, with some further updates then having already come in from the regmap tree). Also some fairly trivial context conflicts in the imx and mcx soc drivers. * tag 'sound-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (280 commits) ALSA: snd-usb: fix stream info output in /proc ALSA: pcm - Add proper state checks to snd_pcm_drain() ALSA: sh: Fix up namespace collision in sh_dac_audio. ALSA: hda/realtek - Fix unused variable compile warning ASoC: sh: fsi: enable chip specific data transfer mode ASoC: sh: fsi: call fsi_hw_startup/shutdown from fsi_dai_trigger() ASoC: sh: fsi: use same format for IN/OUT ASoC: sh: fsi: add fsi_version() and removed meaningless version check ASoC: sh: fsi: use register field macro name on IN/OUT_DMAC ASoC: tegra: Add machine driver for WM8753 codec ALSA: hda - Fix possible races of accesses to connection list array ASoC: OMAP: HDMI: Introduce codec ARM: mx31_3ds: Add sound support ASoC: imx-mc13783 cleanup mx31moboard: Add sound support ASoC: mc13783 codec cleanups ASoC: add imx-mc13783 sound support ASoC: Add mc13783 codec mfd: mc13xxx: add codec platform data ASoC: don't flip master of DT-instantiated DAI links ...
| * | ASoC: tegra: complete Tegra->Tegra20 renamingStephen Warren2012-04-061-2/+2
| |/ | | | | | | | | | | | | | | | | Rename Tegra20-specific Kconfig variables, module filenames, all internal symbol names, clocks, and platform devices, to reflect the fact the DAS and I2S drivers are for a specific HW version. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | ARM: tegra: add pll_x freq table entry for 750MHzStephen Warren2012-04-251-0/+6
|/ | | | | | | | | Some SKUs limit the maximum CPU frequency to 750MHz; see tegra2_pllx_clk_init(). The pll_x frequency table needs an entry for this frequency, or there will be continual log spam from the cpufreq driver attempting to set this rate, yet there being no table entry for it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-03-271-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull "ARM: driver specific updates" from Arnd Bergmann: "These are all specific to some driver. They are typically the platform side of a change in the drivers directory, such as adding a new driver or extending the interface to the platform. In cases where there is no maintainer for the driver, or the maintainer prefers to have the platform changes in the same branch as the driver changes, the patches to the drivers are included as well. A much smaller set of driver updates that depend on other branches getting merged first will be sent later. The new export of tegra_chip_uid conflicts with other changes in fuse.c. In rtc-sa1100.c, the global removal of IRQF_DISABLED conflicts with the cleanup of the interrupt handling of that driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fixed up aforementioned trivial conflicts. * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (94 commits) ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci mmc: sdhci-s3c: add platform data for the second capability ARM: SAMSUNG: support the second capability for samsung-soc ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1 ARM: EXYNOS: Enable MDMA driver regulator: Remove bq24022 regulator driver rtc: sa1100: add OF support pxa: magician/hx4700: Convert to gpio-regulator from bq24022 ARM: OMAP3+: SmartReflex: fix error handling ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API ARM: OMAP3+: SmartReflex: micro-optimization for sanity check ARM: OMAP3+: SmartReflex: misc cleanups ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata() ARM: OMAP3+: hwmod: add SmartReflex IRQs ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register ARM: OMAP3+: SmartReflex: Add a shutdown hook ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP ... Conflicts: arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/fuse.c drivers/rtc/rtc-sa1100.c
| * ARM: tegra: fuse: add functions to access chip revisionOlof Johansson2012-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to get chip revision, and print it out at boot time. Restructure the fuse access to just use cached variables instead of always reading the fuses, and export those variables directly instead of using accessor functions. Add a SKU ID table of currently known values. Based on code originally by Colin Cross <ccross@android.com>. Changes since v1: * Add A01 minor rev support * Don't decode for A03p on anything but T2x Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Demote EMC clock inconsistency BUG to WARNStephen Warren2012-02-261-5/+25
|/ | | | | | | | | When this inconsistency occurs, the system will typically operate without issue, it's just that EMC scaling won't optimally. Convert the BUG_ON to a WARN_ONCE in order to allow the kernel to boot, but still complain. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm/tegra: don't export clk_measure_input_freqPeter De Schrijver2011-12-171-1/+1
| | | | | | | | | | don't export clk_measure_input_freq as its functionality is also available using clk_get_rate(). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm/tegra: prepare clock code for multiple tegra variantsPeter De Schrijver2011-12-171-12/+5
| | | | | | | | | | | | | | | | | Rework the tegra20 clock code to support multiple tegra variants : * remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This functionality should be in clock.c. * remove tegra_sdmmc_tap_delay and export tegra2_sdmmc_tap_delay directly. This feature is handled inside the sdmmc block from tegra30 onwards. So there is no need for support in the clock code beyond tegra20. There are no in tree users of this function. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: tegra2_clocks: don't export some tablesOlof Johansson2011-10-131-4/+4
| | | | | | | | Not used externally, and certainly don't need to be exported. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARM: tegra: tegra2_clocks: 0 -> NULL changesOlof Johansson2011-10-131-17/+17
| | | | | | | | | | | | Fixes a lot of: arch/arm/mach-tegra/tegra2_clocks.c:921:34: warning: Using plain integer as NULL pointer arch/arm/mach-tegra/tegra2_clocks.c:1462:4: warning: Using plain integer as NULL pointer arch/arm/mach-tegra/tegra2_clocks.c:1864:4: warning: Using plain integer as NULL pointer Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARM: tegra: tegra2_clocks: don't cast __iomem pointersOlof Johansson2011-10-131-4/+4
| | | | | | | | | | | | | | Fixes a lot of: arch/arm/mach-tegra/tegra2_clocks.c:180:2: warning: cast removes address space of expression arch/arm/mach-tegra/tegra2_clocks.c:180:2: warning: incorrect type in argument 1 (different base types) arch/arm/mach-tegra/tegra2_clocks.c:180:2: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-tegra/tegra2_clocks.c:180:2: got unsigned int arch/arm/mach-tegra/tegra2_clocks.c:180:2: warning: cast removes address space of expression Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arm: tegra: remove generic disp clock divisor flagRobert Morell2011-07-121-2/+2
| | | | | | | | | | | | Although disp1 and disp2 have 7.1 divisors, their corresponding registers in the clk_rst block are not the interface to program the divisors. Setting the generic DIV_U71 flag may cause the code to attempt to program the clock at a different divisor, which will confuse any code attempting to use that clock since it isn't actually being divided. Signed-off-by: Robert Morell <rmorell@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
* Merge branch 'master' into for-nextJiri Kosina2011-04-261-4/+5
|\ | | | | | | | | Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
| * arm: tegra: fix error check in tegra2_clocks.cNicolas Kaiser2011-04-011-4/+5
| | | | | | | | | | | | | | Checking 'rate < 0' doesn't work because 'rate' is unsigned. Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Signed-off-by: Colin Cross <ccross@android.com>
* | treewide: remove extra semicolonsJustin P. Mattock2011-04-101-1/+1
|/ | | | | Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* ARM: Tegra: Rename clk_dev1/2 to cdev1/2Stephen Warren2011-02-231-6/+6
| | | | | | | | | | | | The ASoC machine driver was written assuming my previous patch to add complete support for these clocks, which named them cdev1/2. Rename the clocks to match that, to avoid churn in the ASoC driver. This rename also makes the clocks more consistent with other Tegra clocks irrespective of any of that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: Tegra: Rename I2S clocks to match driver nameStephen Warren2011-02-231-2/+2
| | | | | | | | The driver is tegra-i2s not just i2s. Rename the clocks to match, so that clk_get_sys can look up by driver name. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: prevent accidental disables of cpu clockColin Cross2011-02-221-0/+25
| | | | | | | | | | | Peripheral clocks that have no clock enable bit in the enable registers have their clk_num set to 0. Bit 0 in the clock enable registers is the CPU clock. Prevent disables on these peripheral clocks from accidentally disabling the CPU clock. Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: clock: Round rate before setting rateColin Cross2011-02-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Call the clock's round_rate op, if it exists, before calling the set_rate op. This will help later when dvfs is added, dvfs needs to know what the final rate will be before the frequency changes. Also requires fixes to the round rate functions to ensure calling round rate and then set rate will not cause the frequency to be rounded down twice. When picking clock divider values, the clock framework picks the closest frequency that is lower than the requested frequency. If the new frequency calculated from the divider value is rounded down, and then passed to set_rate, it will get rounded down again, possibly resulting in a frequency two steps lower than the original requested frequency. Fix the problem by rounding up when calculating the frequency coming out of a clock divider, so if that frequency is requested again, the same divider value will be picked. Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: clock: Refcount periph clock enablesColin Cross2011-02-221-6/+31
| | | | | | | | | Some peripheral clocks share enable bits. Refcount the enables so that calling clk_disable on one clock will not turn off another clock. Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: clock: Miscellaneous clock updatesColin Cross2011-02-211-31/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct max rates for pclk and sclk (Originally fixed by Dima Zavin <dima@android.com>) Correct max rate for plla (Originally fixed by Stephen Warren <swarren@nvidia.com>) Remove unnecessary no-op set_rate on audio clocks Add clock lookup entries for grhost, bsea, and vde clocks Update clock clookup entries for vcp, bsea, and vde clocks Add shared clock entries for sclk and emc Add a virtual cop clock to provide a reset op (Originally fixed by Dima Zavin <dima@android.com>) Pass set_rate on super clocks through to parent Fix pllx frequency table entry for 608 MHz Remove incorrect plla frequency table entries Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Fix clock issues in suspendColin Cross2011-02-211-10/+20
| | | | | | | | | | | | | | | | | | The PLLP registers are now being restored by the low-level resume code, and the CPU may be running off PLLP, so don't touch them during clock resume. Save plld, plls, pllu, and audio clock during suspend (originally fixed by Mayuresh Kulkarni <mkulkarni@nvidia.com>) The lock time for plld is 1000 us, so increase the delay after setting the PLLs. Add a BUG_ON to ensure the size of the suspend context area is correct. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Add function to set SDMMC tap delayColin Cross2011-02-211-0/+19
| | | | | | | | | | | The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clocks: Add emc scalingColin Cross2011-02-211-1/+63
| | | | | | | | | | | | Add clock ops on the emc peripheral clock that call into the emc driver to update the memory controller registers for the new frequency. Tegra has an interlock between the clock controller and the memory controller that prevents the new register values from taking effect until the clock frequency update occurs. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Minor cleanupsColin Cross2011-02-211-2/+0
| | | | | | | | Remove unnecessary uses of #ifdef CONFIG_DEBUG_FS Convert bool assignments from 1 to true Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Add shared bus clock typeColin Cross2011-02-211-0/+116
| | | | | | | | | | | | Some clocks may have multiple downstream users that need to request a higher clock rate. Shared bus clocks provide a unique shared_bus_user clock to each user. The frequency of the bus is set to the highest enabled shared_bus_user clock, with a minimum value set by the shared bus. Drivers can use clk_enable and clk_disable to enable or disable their requirement, and clk_set_rate to set the minimum rate. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: cpufreq: Take an extra reference to pllxColin Cross2011-02-211-4/+11
| | | | | | | | | | During cpu frequency changes, take an extra reference to pllx so that it doesn't turn off and on while the cpu is temporarily on pllp. If the cpu is moved to pllp permanently, pllx will be turned off. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Convert global lock to a lock per clockColin Cross2011-02-211-34/+85
| | | | | | | | | | | Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. This brings the locking in line with the common struct clk patches and should make conversion simple. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Move unshared clk struct members into unionColin Cross2011-02-211-102/+132
| | | | | | | | | Creates a union of a struct for each type of clock to reduce memory usage and clarify which members are used by all clocks and which are used by a single type. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Rearrange static clock tablesColin Cross2011-02-211-55/+51
| | | | | | | | Make the static clocks look more like the array of clocks so they can all be initalized with the same helper function. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Drop CPU dvfsColin Cross2011-02-211-2/+0
| | | | | | | | | The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Don't use PLL lock bitsColin Cross2011-02-201-22/+9
| | | | | | | The PLL lock bits are not reliable, use per-PLL timeouts instead. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Don't BUG on changing an enabled PLLColin Cross2011-02-201-1/+0
| | | | | | | | | | When updating the CPU PLL frequency, keeping the PLL enabled avoids ramping the PLL all the way down and back up again. Remove the BUG_ON in tegra2_pll_clk_set_rate to allow the rate to change while the PLL is enabled. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: enable clk reset for non-peripheral clocksDima Zavin2011-02-201-11/+18
| | | | | | | | | Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Signed-off-by: Dima Zavin <dima@android.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: APB DMA: Enable clock and remove reset.Stephen Warren2011-02-201-0/+6
| | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: clock: Suspend fixes, and add new clocksColin Cross2011-02-091-19/+244
| | | | | | | | | | | | | Save and restore pll and osc state during suspend Add digital audio clocks Update clk dev associations Correct max clock frequencies Add pll_p as additional cpu clock state Add values to plld table Fix register offset for sdmmc4 clock Add blink timer to tegra2_clocks Signed-off-by: Colin Cross <ccross@android.com>
* ARM: tegra: Add prototypes for subsystem suspend functionsColin Cross2011-02-091-0/+1
| | | | Signed-off-by: Colin Cross <ccross@android.com>
* ARM: 6483/1: arm & sh: factorised duplicated clkdev.cJean-Christop PLAGNIOL-VILLARD2010-11-261-2/+1
| | | | | | | | | | | | | factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* tegra: add PCI Express clocksMike Rapoport2010-10-211-0/+48
| | | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
* [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross2010-10-211-171/+607
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
* [ARM] tegra: Add clock supportColin Cross2010-08-051-0/+1359
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: Colin Cross <ccross@android.com>
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