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* Merge branch 'topic/asoc' into for-linusTakashi Iwai2009-09-101-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * topic/asoc: (226 commits) ASoC: au1x: PSC-AC97 bugfixes ASoC: Fix WM835x Out4 capture enumeration ASoC: Remove unuused hw_read_t ASoC: fix pxa2xx-ac97.c breakage ASoC: Fully specify DC servo bits to update in wm_hubs ASoC: Debugged improper setting of PLL fields in WM8580 driver ASoC: new board driver to connect bfin-5xx with ad1836 codec ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI ASoC: davinci: i2c device creation moved into board files ASoC: Don't reconfigure WM8350 FLL if not needed ASoC: Fix s3c-i2s-v2 build ASoC: Make platform data optional for TLV320AIC3x ASoC: Add S3C24xx dependencies for Simtec machines ASoC: SDP3430: Fix TWL GPIO6 pin mux request ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI OMAP: McBSP: Use textual values in DMA operating mode sysfs files ARM: OMAP: DMA: Add support for DMA channel self linking on OMAP1510 ASoC: Select core DMA when building for S3C64xx ...
| * OMAP3: McBSP: Lower the maximum buffersize for McBSP1, 3, 4, 5Peter Ujfalusi2009-08-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | Do not allow applications to use the full buffer found on McBSP1,3,4,5. Using the full buffer in threshold mode causes the McBSP buffer to run dry, which can be observed as channels are switching (in reality the channels are shifting). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| * OMAP: McBSP: Create and export max_(r|t)x_thres propertyEduardo Valentin2009-08-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | This patch export through sysfs two properties to configure maximum threshold for transmission and reception on each mcbsp instance. Also, it exports two helper functions to allow mcbsp users to read this values. Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | Merge branch 'pm-upstream/fixes' of ↵Russell King2009-08-106-74/+186
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm
| * | OMAP3: Overo: add missing pen-down GPIO definitionKevin Hilman2009-08-051-0/+1
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Fix wrong sequence in suspend.Jouni Hogander2009-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Powerdomain previous state is checked after restoring new states in suspend. This patch fixes this problem. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP2/3/4: UART: allow in-order port traversalKevin Hilman2009-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use list_add_tail() when adding discovered UART ports. This is so traversal using list_for_each_entry() will traverse the list in the order they were found. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP2/3/4: UART: Allow per-UART disabling wakeup for serial portsKevin Hilman2009-08-051-58/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch causes the OMAP uarts to honor the sysfs power/wakeup file for IOPAD wakeups. Before the OMAP was always woken up from off mode on a rs232 signal change. This patch also creates a different platform device for each serial port so that the wakeup properties can be control per port. By default, IOPAD wakeups are enabled for each UART. To disable, # echo disabled > /sys/devices/platform/serial8250.0/power/wakeup Where serial8250.0 can be replaced by .1, or .2 to control the other ports. Original idea and original patch from Russ Dill <russ.dill@gmail.com> Cc: Russ Dill <russ.dill@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: Fixed crash bug with serial + suspendTero Kristo2009-08-052-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was possible for an unhandled interrupt to occur if there was incoming serial traffic during wakeup from suspend. This was caused by the code in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time, but not acking its interrupts. Applies on top of PM branch. Use the PM begin/end hooks to ensure that the "serial idle" interrupts are disabled during the suspend path. Also, since begin/end hooks are now used, use the suspend_state that is passed in the begin hook instead of the enter hook as per the platform_suspend_ops docs. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP4: UART: cleanup special case IRQ handlingKevin Hilman2009-08-051-4/+3
| | | | | | | | | | | | | | | | | | | | | Streamline the OMAP4 special IRQ assignments by putting inside normal init loop instead of having a separate loop. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Do not build suspend code if SUSPEND is not enabledKevin Hilman2009-08-051-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: prevent module wakeups from waking IVA2Kevin Hilman2009-08-051-0/+6
| | | | | | | | | | | | | | | | | | | | | By default, prevent functional wakeups from inside a module from waking up the IVA2. Let DSP Bridge code handle this when loaded. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Clear pending PRCM reset flags on initKevin Hilman2009-08-051-0/+9
| | | | | | | | | | | | | | | | | | | | | Any pending reset flags can prevent retention. Ensure they are all cleared during boot. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Ensure PRCM interrupts are cleared at bootKevin Hilman2009-08-051-0/+3
| | | | | | | | | | | | | | | | | | | | | Any pending PRCM interrupts can prevent retention. Ensure they are cleared during boot. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: CM_REGADDR macros using wrong nameKevin Hilman2009-08-051-3/+3
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP2/3: PM: make PM __init calls staticKevin Hilman2009-08-053-5/+2
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* | | Merge branch 'omap_fixes_31' of git://git.pwsan.com/linux-2.6Russell King2009-08-1024-180/+575
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| * | | OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSBPaul Walmsley2009-07-242-18/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS, USBHOST, and HSOTGUSB devices. These devices are both interconnect initiators and targets. Without this patch, clk_enable()s on clocks for these modules can be very high latency (potentially up to ~200 milliseconds) and message such as the following are generated: Clock usbhost_48m_fck didn't enable in 100000 tries Two bugs are fixed by this patch. First, OMAP hardware only supports target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips should not wait for these clocks to enable. So, split the appropriate clocks into ES1 and ES2+ variants, so that kernels running on ES1 devices won't try to wait. Second, the current heuristic in omap2_clk_dflt_find_idlest() will fail for these clocks. It assumes that the CM_IDLEST bit to wait upon is the same as the CM_*CLKEN bit, which is false[1]. Fix by implementing custom clkops .find_idlest function pointers for the appropriate clocks that return the correct slave IDLEST bit shift. This was originally fixed in the linux-omap kernel during 2.6.29 in a slightly different manner[2][3]. In the medium-term future, all of the module IDLEST code will eventually be moved to the omap_hwmod code. Problem reported by Jarkko Nikula <jhnikula@gmail.com>: http://marc.info/?l=linux-omap&m=124306184903679&w=2 ... 1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the DSS case). 2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq. 3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com>
| * | | OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST registerPaul Walmsley2009-07-242-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE [1]. Fix by implementing a custom clkops .find_idlest function to return the correct slave IDLEST register. ... 1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1 (Rev. V) Technical Reference Manual, tables 4-99 and 4-105. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | OMAP2/3 clock: split, rename omap2_wait_clock_ready()Paul Walmsley2009-07-243-77/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not handled by the current omap2_wait_clock_ready() code. In preparation for patches that fix the unusual devices, rename the function omap2_wait_clock_ready() to omap2_wait_module_ready() and split it into three parts: 1. A clkops-specific companion clock return function (by default, omap2_clk_dflt_find_companion()) 2. A clkops-specific CM_IDLEST register address and bit shift return function (by default, omap2_clk_dflt_find_idlest()) 3. Code to wait for the CM to indicate that the module is ready (omap2_cm_wait_idlest()) Clocks can now specify their own custom find_companion() and find_idlest() functions; used in subsequent patches. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | OMAP3 SDRC: Move the clk stabilization delay to the right placeRajendra Nayak2009-07-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock stabilization delay post a M2 divider change is needed even before a SDRC interface clock re-enable and not only before jumping back to SDRAM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83MhzRajendra Nayak2009-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the CORE dpll scaling sequence which was errouneously clearing some bits in the SDRC DLLA CTRL register and hence causing a freeze. The issue was observed only on platforms which scale CORE dpll to < 83Mhz and hence program the DLL in fixed delay mode. Issue reported by Limei Wang <E12499@motorola.com>, with debugging assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish Ghongdemath <girishsg@ti.com>. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: Limei Wang <E12499@motorola.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Girish Ghongdemath <girishsg@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: updated patch description to include collaboration credits]
| * | | OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on bootPaul Walmsley2009-07-242-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum (34xx erratum 1.150) that can cause memory corruption if PWDENA is enabled. Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>. Tested on BeagleBoard rev C2. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
| * | | OMAP3: Setup MUX settings for SDRC CKE signalsJean Pihet2009-07-245-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches ensures the MUX settings are correct for the SDRC CKE signals to SDRAM. This allows the self-refresh to work when 2 chip-selects are in use. A warning is thrown away in case the initial muxing is incorrect, in order to track faulty or old-dated bootloaders. Note: The CONFIG_OMAP_MUX and CONFIG_OMAP_MUX_WARNINGS options must be enabled for the mux code to have effect. Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | OMAP3 SDRC: add support for 2 SDRAM chip selectsJean Pihet2009-07-2417-76/+195
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2 SDRAM parts connected to the SDRC. This patch adds the following: - add a new argument of type omap_sdrc_params struct* to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params - adapted the OMAP boards files to the new prototype of omap2_init_common_hw - add the SDRC 2nd CS registers offsets defines - adapt the sram sleep code to configure the SDRC for the 2nd CS Note: If the 2nd param to omap2_init_common_hw is NULL, then the parameters are not programmed into the SDRC CS1 registers Tested on 3430 SDP and Beagleboard rev C2 and B5, with suspend/resume and frequency changes (cpufreq). Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | Merge branch 'omap-fixes' of ↵Russell King2009-08-103-1/+12
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
| * | | OMAP2/3: mmc-twl4030: Free up MMC regulators while cleaning upRoger Quadros2009-08-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | twl_mmc_cleanup() must free up the regulators that were allocated by twl_mmc_late_init(). This eliminates the below error when 'omap_hsmmc' module is repeatedly loaded and unloaded. "sysfs: cannot create duplicate filename '/devices/platform /mmci-omap-hs.0/microamps_requested_vmmc'" Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | OMAP3: RX51: Define TWL4030 USB transceiver in board fileRoger Quadros2009-08-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add OTG transceiver to RX51 platform data to prevent kernel NULL pointer dereference during MUSB initialisation. Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | OMAP3: Overo: Fix smsc911x platform device resource valueSergio Aguirre2009-08-101-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes a wrong setting of resource parameter list in SMSC911x platform driver data structure for Overo case. This fixes folowing warning when compiling for Overo board: warning: initialization from incompatible pointer type Introduced since commit id: commit 172ef275444efa12d834fb9d1b1acdac92db47f7 Author: Steve Sakoman <sakoman@gmail.com> Date: Mon Feb 2 06:27:49 2009 +0000 ARM: Add SMSC911X support to Overo platform (V2) Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | USB: musb: fix the nop registration for OMAP3EVMGupta, Ajay Kumar2009-08-072-21/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP3EVM uses ISP1504 phy which doesn't require any programming and thus has to use NOP otg transceiver. Cleanups being done: - Remove unwanted code in usb-musb.c file - Register NOP in OMAP3EVM board file using usb_nop_xceiv_register(). - Select NOP_USB_XCEIV for OMAP3EVM boards. - Don't enable TWL4030_USB in omap3_evm_defconfig Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Eino-Ville Talvala <talvala@stanford.edu> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | | ARM: includecheck fix: mach-omap2/mcbsp.cJaswinder Singh Rajput2009-07-251-1/+0
|/ / | | | | | | | | | | | | | | | | | | | | fix the following 'make includecheck' warning: arch/arm/mach-omap2/mcbsp.c: mach/irqs.h is included more than once. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Acked-by: Eduardo Valentin <eduardo.valentin@nokia.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | OMAP3: RX51: Use OneNAND sync read / writeAdrian Hunter2009-06-231-0/+1
| | | | | | | | | | | | | | Use OneNAND sync read / write Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP2/3: gpmc-onenand: correct use of async timingsAdrian Hunter2009-06-231-2/+19
| | | | | | | | | | | | | | | | | | | | Use async timings when sync timings are not requested. Also ensure that OneNAND is in async mode when async timings are used. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP2/3: Add omap_type() for determining GP/EMU/HSKevin Hilman2009-06-231-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_type() function is added and returns the DEVICETYPE field of the CONTROL_STATUS register. The result can be used for conditional code based on whether device is GP (general purpose), EMU or HS (high security). Also move the type defines so omap1 code compile does not require ifdefs for sections using these defines. This code is needed for the following fix to set the SRAM size correctly for HS omaps. Also at least PM and watchdog code will need this function. Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP2/3: omap mailbox: platform_get_irq() error ignoredRoel Kluin2009-06-231-3/+3
| | | | | | | | | | | | | | | | | | platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq is unsigned, so the error was not noticed. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP2/3: mmc-twl4030: use correct controller in twl_mmc23_set_powerGrazvydas Ignotas2009-06-231-1/+12
|/ | | | | | | | | twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which breaks MMC3. Find the right controller to use instead. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into develRussell King2009-06-205-57/+154
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| * OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisonsRoel Kluin2009-06-192-2/+2
| | | | | | | | | | | | | | | | with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLLPaul Walmsley2009-06-191-0/+12
| | | | | | | | | | | | | | | | | | | | Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz). Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3: Add support for DPLL3 divisor values higher than 2Tero Kristo2009-06-192-9/+8
| | | | | | | | | | | | Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
| * OMAP3 SRAM: convert SRAM code to use macros rather than magic numbersPaul Walmsley2009-06-191-15/+38
| | | | | | | | | | | | | | Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 SRAM: add more comments on the SRAM codePaul Walmsley2009-06-191-21/+24
| | | | | | | | | | | | Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changePaul Walmsley2009-06-192-3/+9
| | | | | | | | | | | | | | | | | | Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: add a short delay when lowering CORE clk ratePaul Walmsley2009-06-192-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: initialize SDRC timings at kernel startPaul Walmsley2009-06-192-3/+36
| | | | | | | | | | | | | | | | On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: remove wait for DPLL3 M2 clock to stabilizePaul Walmsley2009-06-191-3/+0
| | | | | | | | | | | | | | | | The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | ARM: OMAP4: SMP: Enable SMP support for OMAP4430Santosh Shilimkar2009-06-091-0/+4
| | | | | | | | | | | | This patch enables SMP on OMAP4430 SDP platform. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | ARM: OMAP4: SMP: Add mpu timer support for OMAP4430Santosh Shilimkar2009-06-092-0/+38
| | | | | | | | | | | | | | | | This patch adds SMP platform specific parts for local(mpu) timer support for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the MPU domain. These timers are not in wakeup domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | ARM: OMAP4: SMP: Add OMAP4430 SMP board filesSantosh Shilimkar2009-06-092-0/+224
| | | | | | | | | | | | | | | | This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | Merge branch 'for-next' of ↵Russell King2009-05-2948-806/+4973
|\ \ | |/ | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel Conflicts: arch/arm/Makefile
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