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* ARM: OMAP4: SMP: Enable SMP support for OMAP4430Santosh Shilimkar2009-06-091-0/+4
| | | | | | This patch enables SMP on OMAP4430 SDP platform. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: OMAP4: SMP: Add mpu timer support for OMAP4430Santosh Shilimkar2009-06-092-0/+38
| | | | | | | | This patch adds SMP platform specific parts for local(mpu) timer support for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the MPU domain. These timers are not in wakeup domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: OMAP4: SMP: Add OMAP4430 SMP board filesSantosh Shilimkar2009-06-092-0/+224
| | | | | | | | This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* Merge branch 'for-next' of ↵Russell King2009-05-2948-806/+4973
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel Conflicts: arch/arm/Makefile
| * Merge branch 'omap4' into for-nextTony Lindgren2009-05-288-6/+179
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| | * ARM: OMAP4: Add support for 4430 SDPSantosh Shilimkar2009-05-283-1/+102
| | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Makefile and Kconfig entries for OMAP4. The OMAP4430 SDP board file supports only minimal set of drivers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP4: Add minimal support for omap4Santosh Shilimkar2009-05-285-5/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support for OMAP4. The platform and machine specific headers and sources updated for OMAP4430 SDP platform. OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | Merge branch 'omap3-boards' into for-nextTony Lindgren2009-05-2811-200/+1100
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| | * ARM: OMAP3: pandora: add support for mode devicesGrazvydas Ignotas2009-05-281-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | Add support for keypad, GPIO keys and LEDs. Also enable hardware debounce feature for GPIO keys. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: Add omap3 EVM supportSyed Mohammed Khasim2009-05-283-0/+335
| | | | | | | | | | | | | | | | | | | | | Add omap3 EVM support Signed-off-by: Syed Mohammed Khasim <khasim@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: Add support for OMAP3 Zoom2 boardVikram Pandita2009-05-284-1/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates the minimal OMAP3 Zoom2 board support. Signed-off-by: Mikkel Christensen <mlc@ti.com> Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: RX51: Connect VAUX3 to MMC2Adrian Hunter2009-05-281-3/+27
| | | | | | | | | | | | | | | | | | | | | Connect VAUX3 to MMC2 Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: pandora: setup regulator framework for MMCGrazvydas Ignotas2009-05-281-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup regulators for MMC1 and MMC2 to get those SD slots working again. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> CC: David Brownell <david-b@pacbell.net> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: Initialize regulators for Beagle and OveroDavid Brownell2009-05-282-28/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize regulators for Beagle and Overo. Patch is based on earlier patches posted to linux-omap mailing list. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: mmc-twl4030 uses regulator frameworkDavid Brownell2009-05-282-168/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Decouple the HSMMC glue from the twl4030 as the only regulator provider, using the regulator framework instead. This makes the glue's "mmc-twl4030" name become a complete misnomer ... this code could probably all migrate into the HSMMC driver now. Tested on 3430SDP (SD and low-voltage MMC) and Beagle (SD), plus some other boards (including Overo) after they were converted to set up MMC regulators properly. Eventually all boards should just associate a regulator with each MMC controller they use. In some cases (Overo MMC2 and Pandora MMC3, at least) that would be a fixed-voltage regulator with no real software control. As a temporary hack (pending regulator-next updates to make the "fixed.c" regulator become usable) there's a new ocr_mask field for those boards. Patch updated with a fix for disabling vcc_aux by Adrian Hunter <adrian.hunter@nokia.com> Cc: Pierre Ossman <drzeus-list@drzeus.cx> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | Merge branch 'omap3-upstream' into for-nextTony Lindgren2009-05-288-26/+348
| |\ \ | | |/ | | | | | | | | | Conflicts: arch/arm/mach-omap2/serial.c
| | * ARM: OMAP3: Initialize more devices for LDPTony Lindgren2009-05-281-1/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on an earlier patches by Stanley.Miao <stanley.miao@windriver.com> and Nishant Kamat <nskamat@ti.com>. Note that at the ads7846 support still needs support for vaux_control for the touchscreen to work. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: ZOOM MDK: Add FB support to board fileImre Deak2009-05-281-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on an earlier patch by Stanley.Miao <stanley.miao@windriver.com> with board-*.c changes split to avoid conflicts with other device updates. Cc: linux-fbdev-devel@lists.sourceforge.net Signed-off-by: Stanley.Miao <stanley.miao@windriver.com> Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: SDRC: add timing data for Qimonda HYB18M512160AF-6Paul Walmsley2009-05-282-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on the OMAP3430SDP boards. Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying the chip used on 3430SDP. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP3: SDRC: add timing data for Micron MT46H32M32LF-6, v2Paul Walmsley2009-05-284-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the OMAP3 Beagle and EVM boards. Original timing data is from the Micron datasheet PDF downloaded from: http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying the chips used on Beagle & OMAP3EVM. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Serial: Remove arch_initcall dependencyVikram Pandita2009-05-281-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform_device_register() for serial device to omap_serial_init() There is no need to have arch_initcall() dependency in serial as already board files call the function omap_serial_init() Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | Merge branch 'omap-upstream' into for-nextTony Lindgren2009-05-286-250/+677
| |\ \ | | |/ | | | | | | | | | Conflicts: arch/arm/mach-omap2/Makefile
| | * ARM: OMAP2: 2430SDP: Add FB support to board fileImre Deak2009-05-281-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on an earlier patch by Hunyue Yau <hyau@mvista.com> with board-*.c changes split to avoid conflicts with other device updates. Cc: linux-fbdev-devel@lists.sourceforge.net Signed-off-by: Hunyue Yau <hyau@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Add generic smc91x support when connected to GPMCTony Lindgren2009-05-285-254/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the board-rx51 smc91x code to be generic and make the boards to use it. This allows future recalculation of the timings when the source clock gets scaled. Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL. Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing calculations. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Add generic onenand support when connected to GPMCJuha Yrjola2009-05-283-0/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic onenand support when connected to GPMC and make the boards to use it. The patch has been modified to make it more generic to support all the boards with GPMC. The patch also remove unused prototype for omap2_onenand_rephase(void). Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC and setting the GPMC timings in the bootloader. Setting the GPMC timings in the bootloader will not allow supporting frequency scaling for the onenand source clock. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Reorganize Makefile to add omap4 supportTony Lindgren2009-05-251-3/+8
| | | | | | | | | | | | | | | | | | | | | We don't necessarily want to compile in irq.o and sdrc.o for omap4. Also, clock and prcm may not be implemented initially. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Remove OMAP_CM_REGADDRTony Lindgren2009-05-253-5/+4
| | | | | | | | | | | | | | | | | | Processor specific macros should be used instead. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Remove OMAP_PRM_REGADDR and OMAP2_PRM_BASETony Lindgren2009-05-258-97/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove OMAP_PRM_REGADDR and use processor specific defines instead. Also fold in a patch from Kevin Hilman to add _OFFSET #defines for the PRCM registers to be used with the prm_[read|write]_* macros. These are used extensively in the forthcoming OMAP PM support. Also remove now unused OMAP2_PRM_BASE. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * ARM: OMAP2/3: Remove OMAP2_32KSYNCT_BASETony Lindgren2009-05-252-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use processor specific defines instead. As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK calling sched_clock before we have things initialized: http://patchwork.kernel.org/patch/15810/ Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | OMAP3: PM: prevent module wakeups from waking IVA2Kevin Hilman2009-05-282-0/+8
| | | | | | | | | | | | | | | | | | | | | By default, prevent functional wakeups from inside a module from waking up the IVA2. Let DSP Bridge code handle this when loaded. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Clear pending PRCM reset flags on initKevin Hilman2009-05-281-0/+9
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Ensure PRCM interrupts are cleared at bootKevin Hilman2009-05-281-0/+3
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Ensure MUSB block can idle when driver not loadedPeter 'p2' De Schrijver2009-05-282-2/+20
| | | | | | | | | | | | | | | | | | | | | Otherwise, bootloaders may leave MUSB in a state which prevents retention. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: D2D clockdomain supports SW supervised transitionsKevin Hilman2009-05-281-1/+1
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM initKevin Hilman2009-05-284-4/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework and ensure that auto-idle bits are set for these clocks during PRCM init. Also add omap3_d2d_idle() function called durint PRCM setup which ensures D2D pins are MUX'd correctly to enable retention for standalone (no-modem) devices. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP: UART: Add sysfs interface for adjusting UART sleep timeoutJouni Hogander2009-05-281-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes it possible to change uart sleep timeout. New sysfs entry is added (/sys/devices/platform/serial8250.<uart>/sleep_timeout) Writing zero will disable the timeout feature and prevent UART clocks from being disabled. Also default timeout is increased to 5 second to make serial console more usable. Original patch was written by Tero Kristo. Cc: Tero Kristo <Tero.Kristo@nokia.com> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: UART: disable clocks when idle and off-mode supportKevin Hilman2009-05-283-25/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the UART clocks to be disabled when the OMAP UARTs are inactive, thus permitting the chip to hit retention in idle. After the expiration of an activity timer, each UART is allowed to disable its clocks so the system can enter retention. The activity timer is (re)activated on any UART interrupt, UART wake event or any IO pad wakeup. The actual disable of the UART clocks is done in the 'prepare_idle' hook called from the OMAP idle loop. While the activity timer is active, the smart-idle mode of the UART is also disabled. This is due to a "feature" of the UART module that after a UART wakeup, the smart-idle mode may be entered before the UART has communicated the interrupt, or upon TX, an idle mode may be entered before the TX FIFOs are emptied. Upon suspend, the 'prepare_suspend' hook cancels any pending activity timers and allows the clocks to be disabled immediately. In addition, upon disabling clocks the UART state is saved in case of an off-mode transition while clocks are off. Special thanks to Tero Kristo for the initial ideas and first versions of UART idle support, and to Jouni Hogander for extra testing and bugfixes. Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810) Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP3: PM: Force IVA2 into idle during bootupKevin Hilman2009-05-281-0/+50
| | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP: Add new function to check wether there is irq pendingJouni Hogander2009-05-282-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add common omap2/3 function to check wether there is irq pending. Switch to use it in omap2 pm code instead of its own. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | OMAP2/3: PM: push core PM code from linux-omapKevin Hilman2009-05-2811-115/+1789
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to sync the core linux-omap PM code with mainline. This code has evolved and been used for a while the linux-omap tree, but the attempt here is to finally get this into mainline. Following this will be a series of patches from the 'PM branch' of the linux-omap tree to add full PM hardware support from the linux-omap tree. Much of this PM core code was written by Jouni Hogander with significant contributions from Paul Walmsley as well as many others from Nokia, Texas Instruments and linux-omap community. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | Revert "ARM: OMAP: Mask interrupts when disabling interrupts, v2"Kevin Hilman2009-05-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5461af5af5c6a7fee78978aafe720541bf3a2f55. Adding a disable hook to the irq_chip is not the way to fix the problem being addressed by this patch. Instead, we need to fix support for [enable|disable]_irq_wake(). Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2009-05-265-77/+107
| |\ \ | | | | | | | | | | | | for-next
| | * | OMAP2xxx clock: rename clk_init_one() to clk_preinit()Paul Walmsley2009-05-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rename clk_init_one() to clk_preinit() to distinguish its function from clk_init() and the individual struct clk init functions. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 clock: lessen amount of noisy messagesArtem Bityutskiy2009-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On our system we see the following messages: Disabling unused clock "gpt2_ick" Disabling unused clock "gpt3_ick" Disabling unused clock "gpt4_ick" Disabling unused clock "gpt5_ick" ... The messages have KERN_INFO level and if you have serial console, they normally go there. I do not think it is good idea to print that much stuff there. Moreover, messages are not properly prefixed and for mortals it is not immeadietly clear where they come from. Let's give them debugging level instead. Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: trimmed debugging output in patch description]
| | * | OMAP3 clock: use pr_debug() rather than pr_info() in some clock change codePaul Walmsley2009-05-122-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHzPaul Walmsley2009-05-122-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 SRAM: renumber registers to make space for argument passingPaul Walmsley2009-05-121-57/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 SDRC: initialize SDRC_POWER at bootPaul Walmsley2009-05-121-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize SDRC_POWER to a known-good setting when the kernel boots. Necessary since some bootloaders don't initialize SDRC_POWER properly. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency changePaul Walmsley2009-05-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh mode. This prevents the SDRC from attempting to power off the SDRAM, which can cause the system to hang. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP3 clock: add interconnect barriers to CORE DPLL M2 changePaul Walmsley2009-05-121-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Where necessary, add interconnect barriers to force posted writes to complete before continuing. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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