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* ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driverSuman Anna2014-07-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 7be914f {ARM: OMAP3: PRM/CM: Cleanup unused header} removed some of the macros used by the TI DSP/Bridge driver. This fixes the following build errors when trying to build DSP/Bridge driver (disabled at present), otherwise results in the following build errors: drivers/staging/tidspbridge/core/tiomap3430.c:531:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430.c:531:31: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430.o] Error 1 make[3]: *** Waiting for unfinished jobs.... drivers/staging/tidspbridge/core/tiomap_io.c: In function 'sm_interrupt_dsp': drivers/staging/tidspbridge/core/tiomap_io.c:404:31: error: 'OMAP3430_AUTO_IVA2_DPLL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap_io.c:404:31: note: each undeclared identifier is reported only once for each function it appears in drivers/staging/tidspbridge/core/tiomap_io.c:414:12: error: 'OMAP3430_IVA2_DPLL_FREQSEL_SHIFT' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap_io.c:415:12: error: 'OMAP3430_EN_IVA2_DPLL_SHIFT' undeclared (first use in this function) make[3]: *** [drivers/staging/tidspbridge/core/tiomap_io.o] Error 1 drivers/staging/tidspbridge/core/tiomap3430_pwr.c: In function 'dsp_clk_wakeup_event_ctrl': drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: error: 'OMAP3430_GRPSEL_GPT5_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:442:19: note: each undeclared identifier is reported only once for each function it appears in drivers/staging/tidspbridge/core/tiomap3430_pwr.c:455:19: error: 'OMAP3430_GRPSEL_GPT6_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:468:19: error: 'OMAP3430_GRPSEL_GPT7_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:481:19: error: 'OMAP3430_GRPSEL_GPT8_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:494:19: error: 'OMAP3430_GRPSEL_MCBSP1_MASK' undeclared (first use in this function) drivers/staging/tidspbridge/core/tiomap3430_pwr.c:546:19: error: 'OMAP3430_GRPSEL_MCBSP5_MASK' undeclared (first use in this function) make[3]: *** [drivers/staging/tidspbridge/core/tiomap3430_pwr.o] Error 1 make[2]: *** [drivers/staging/tidspbridge] Error 2 Fixes: 7be914f (ARM: OMAP3: PRM/CM: Cleanup unused header) Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP3: PRM/CM: Cleanup unused headerRajendra Nayak2013-07-211-632/+0
| | | | | | | | Cleanup unused parts of the PRM and CM regbit headers leaving only whats used. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP3: clock: Add 3xxx data using common struct clkRajendra Nayak2012-11-121-0/+31
| | | | | | | | | | | | | | | The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck" clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck aliases; replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflow macros and parent name lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros] Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP3: hwmod data: add sad2d hwmodTero Kristo2012-09-231-0/+2
| | | | | | | | | | | SAD2D stands for the die to die interface, and is used for communicating with the optional stacked modem. This hwmod is added in preparation for the d2d_idle move from pm34xx.c to hwmod data. Signed-off-by: Tero Kristo <t-kristo@ti.com> [paul@pwsan.com: SAD2D presumably doesn't exist on non-OMAP34xx/OMAP36xx, so only add it to the OMAP34xx/OMAP36xx lists] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP3: hwmod data: fix iva2 reset infoTero Kristo2012-09-031-0/+1
| | | | | | | | | IVA2 hwmod resets were missing the status bit offsets. Also, as the hwmod itself didn't have prcm info at all, resetting iva hwmod was accessing some bogus memory addresses. Added both infos to fix this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP AM35xx: clock and hwmod data: fix UART4 dataPaul Walmsley2012-06-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | Add missing terminators to the arrays of IRQ, DMA, and address space structure records in the AM35xx UART4 hwmod data. Without these terminators, the following warnings appear on boot: omap_uart.3: failed to claim resource 58 omap_device: omap_uart: build failed (-16) WARNING: at /home/paul/linux/arch/arm/mach-omap2/serial.c:375 omap_serial_init_port+0x198/0x284() Could not build omap_device for omap_uart: uart4. Also, AM35xx uart4_fck has an incorrect parent clock pointer. Fix it and clean up a whitespace issue. Fix some incorrectly-named macros related to AM35xx UART4. Cc: Kyle Manna <kyle.manna@fuel7.com> Cc: Mark A. Greer <mgreer@animalcreek.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Mark A. Greer <mgreer@animalcreek.com>
* ARM: OMAP3: Fix CM register bit masksRajendra Nayak2012-05-071-2/+2
| | | | | | | | The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL register are 3 bits wide. Fix the MASK definition accordingly. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: clockdomains: add OMAP4 PRCM data and OMAP4 supportPaul Walmsley2010-12-211-0/+11
| | | | | | | | | | | | | | | | | | Add PRCM partition, CM instance register address offset, and clockdomain register address offset to each OMAP4 struct clockdomain record. Add OMAP4 clockdomain code to use this new data to access registers properly. While here, clean up some nearby clockdomain code to allocate auto variables in my recollection of Linus's preferred style. The autogeneration scripts have been updated. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific filesPaul Walmsley2010-12-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Acked-by: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* OMAP3: PRCM: Consider UART4 for 3630 chip in prcm_setup_regsGovindraj.R2010-09-291-0/+2
| | | | | | | | | | | | | To standarize among other uarts (1 to 3), we shall now: - Enable uart4 autodile bit. - Enable uart4 wakeup in PER. - Allow uart4 to wakeup the MPU. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* OMAP3 PRCM: convert OMAP3 PRCM macros to the _SHIFT/_MASK suffixesPaul Walmsley2010-05-201-111/+111
| | | | | | | | | | | Fix all of the remaining OMAP3 PRCM register shift/bitmask macros that did not use the _SHIFT/_MASK suffixes to use them. This makes the use of these macros consistent. It is intended to reduce error, as code can be inspected visually by reviewers to ensure that bitshifts and bitmasks are used in the appropriate places. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
* OMAP3 clock: add support for 192Mhz DPLL4M2 outputVishwanath BS2010-02-241-0/+2
| | | | | | | | | | | | | | | In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Introduce 3630 DPLL4 HSDivider changesVishwanath BS2010-02-241-0/+5
| | | | | | | | | | | | Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: introduce DPLL4 JtypeRichard Woodruff2010-02-241-0/+5
| | | | | | | | | | | | | | | | DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: added some comments; updated copyrights and credits; fixed some style issues] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* AM35xx: Add clock support for new modules on AM35xxRanjith Lohithakshan2010-02-241-0/+10
| | | | | | | | | | | | This patch adds clock support for the following AM35xx modules - Ethernet MAC - CAN Controller (HECC) - New MUSB OTG Controller with integrated Phy - Video Processing Front End (VPFE) - Additional UART (UART4) Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: Clock: Added IDLEST definitions for SGXTero Kristo2010-02-241-0/+4
| | | | | | | | Added definitions for OMAP3430ES2_ST_SGX_SHIFT and OMAP3430ES2_ST_SGX_MASK as these were missing. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: clock: use std _MASK suffix for CM_FCLKEN_IVA2 definesKevin Hilman2010-02-241-1/+1
| | | | | | | | Add _MASK suffix to CM_FCLKEN_IVA2 bitfieds to conform with the rest of the usage in cm-regbits-34xx.h of using _SHIFT and _MASK suffixes. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM initKevin Hilman2009-05-281-0/+14
| | | | | | | | | | | | Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework and ensure that auto-idle bits are set for these clocks during PRCM init. Also add omap3_d2d_idle() function called durint PRCM setup which ensures D2D pins are MUX'd correctly to enable retention for standalone (no-modem) devices. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* [ARM] OMAP2 PRCM: clean up CM_IDLEST bitsPaul Walmsley2009-02-081-25/+71
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly marked as being OMAP2xxx-wide, when they were actually 2420-specific. Also, originally when the PRCM register macros were defined, bit shift macros used a "_SHIFT" suffix, and mask macros used none. This became a source of bugs and confusion, as the mask macros were mistakenly used for shift values. Gradually, the mask macros have been updated, piece by piece, to add a "_MASK" suffix on the end to clarify. This patch applies this change to the CM_IDLEST_* register bits. The patch also adds a few bits that were missing, mostly from the 3430ES1 to ES2 revisions. linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77, e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of 9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1 Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP34XX: Add miscellaneous definitions related to 34xxJouni Hogander2009-02-081-0/+7
| | | | | | Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP: Add CSI2 clock struct for handling it with clock APISergio Aguirre2009-02-081-0/+2
| | | | | | | | | | | Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2: Fix definition of SGX clock register bitsDaniel Stone2009-02-081-2/+6
| | | | | | | | | | | | | | | The GFX/SGX functional and interface clocks have different masks, for some unknown reason, so split EN_SGX_SHIFT into one each for fclk and iclk. Correct according to the TRM and the far more important 'does this actually work at all?' metric. linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e. Signed-off-by: Daniel Stone <daniel.stone@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: fix 96MHz clocksPaul Walmsley2009-02-081-2/+6
| | | | | | | | | | | | | | | | Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks. The 96MHz portion of the clock tree should now have reasonable fidelity to the 34xx TRM Rev I. One remaining question mark: it's not clear exactly which 96MHz source clock the USIM uses. This patch sticks with the previous setting, which seems reasonable. linux-omap source commit is 15c706e8179ce238c3ba70a25846a36b73bd2359. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clockdomain: Encode OMAP2/3 clockdomainsPaul Walmsley2008-08-191-11/+31
| | | | | | | | | | | Add clockdomain definitions for OMAP24xx and OMAP34xx chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functionsPaul Walmsley2008-07-031-7/+11
| | | | | | | | | | | | | | | | This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Add fuctional clock enabler for iva2Hiroshi DOYU2008-05-091-0/+1
| | | | | | | | Add fuctional clock enabler for iva2 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-141-0/+4
| | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Add register access for 34xxTony Lindgren2008-04-141-0/+669
This patch adds register access for 34xx power and clock management. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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