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* omap3: clock: Fix the DPLL freqsel computationsRajendra Nayak2009-11-171-1/+1
| | | | | | | | | | | | | | | | | Fix the freqsel value computation. Use n instead of (n+1) The formula in the TRM uses a zero-based N, hence the (n+1); however at this point in the clock34xx.c code, N is one-based. Hayati Bayrakdar <h-bayrakdar@ti.com> and Nishanth Menon <nm@ti.com> helped track down this bug. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: modified commit message] Cc: Hayati Bayrakdar <h-bayrakdar@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* omap: Lock DPLL5 at bootRajendra Nayak2009-10-051-0/+35
| | | | | | | | | | | | | | | Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and USBTLL f-clock are the only users of this DPLL, and 120MHz is is the only recommended rate for these clocks. With this patch, the 60 MHz ULPI clock is generated correctly. Tested on an OMAP3430 SDP. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP3 clock: Fixed processing of bootarg 'mpurate'Sanjeev Premi2009-09-031-8/+9
| | | | | | | | The argument 'mpurate' had no effect on the MPU frequency. This patch fixes the same. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSBPaul Walmsley2009-07-241-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS, USBHOST, and HSOTGUSB devices. These devices are both interconnect initiators and targets. Without this patch, clk_enable()s on clocks for these modules can be very high latency (potentially up to ~200 milliseconds) and message such as the following are generated: Clock usbhost_48m_fck didn't enable in 100000 tries Two bugs are fixed by this patch. First, OMAP hardware only supports target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips should not wait for these clocks to enable. So, split the appropriate clocks into ES1 and ES2+ variants, so that kernels running on ES1 devices won't try to wait. Second, the current heuristic in omap2_clk_dflt_find_idlest() will fail for these clocks. It assumes that the CM_IDLEST bit to wait upon is the same as the CM_*CLKEN bit, which is false[1]. Fix by implementing custom clkops .find_idlest function pointers for the appropriate clocks that return the correct slave IDLEST bit shift. This was originally fixed in the linux-omap kernel during 2.6.29 in a slightly different manner[2][3]. In the medium-term future, all of the module IDLEST code will eventually be moved to the omap_hwmod code. Problem reported by Jarkko Nikula <jhnikula@gmail.com>: http://marc.info/?l=linux-omap&m=124306184903679&w=2 ... 1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the DSS case). 2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq. 3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com>
* OMAP3 SDRC: add support for 2 SDRAM chip selectsJean Pihet2009-07-241-9/+28
| | | | | | | | | | | | | | | | | | | | | | Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2 SDRAM parts connected to the SDRC. This patch adds the following: - add a new argument of type omap_sdrc_params struct* to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params - adapted the OMAP boards files to the new prototype of omap2_init_common_hw - add the SDRC 2nd CS registers offsets defines - adapt the sram sleep code to configure the SDRC for the 2nd CS Note: If the 2nd param to omap2_init_common_hw is NULL, then the parameters are not programmed into the SDRC CS1 registers Tested on 3430 SDP and Beagleboard rev C2 and B5, with suspend/resume and frequency changes (cpufreq). Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: Add support for DPLL3 divisor values higher than 2Tero Kristo2009-06-191-6/+3
| | | | | | Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
* OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changePaul Walmsley2009-06-191-2/+2
| | | | | | | | | Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: add a short delay when lowering CORE clk ratePaul Walmsley2009-06-191-2/+28
| | | | | | | | | | | | | When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: initialize SDRC timings at kernel startPaul Walmsley2009-06-191-3/+0
| | | | | | | | On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM initKevin Hilman2009-05-281-0/+3
| | | | | | | | | | | | Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework and ensure that auto-idle bits are set for these clocks during PRCM init. Also add omap3_d2d_idle() function called durint PRCM setup which ensures D2D pins are MUX'd correctly to enable retention for standalone (no-modem) devices. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2009-05-261-6/+14
|\ | | | | | | for-next
| * OMAP2xxx clock: rename clk_init_one() to clk_preinit()Paul Walmsley2009-05-121-1/+1
| | | | | | | | | | | | Rename clk_init_one() to clk_preinit() to distinguish its function from clk_init() and the individual struct clk init functions. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: use pr_debug() rather than pr_info() in some clock change codePaul Walmsley2009-05-121-4/+4
| | | | | | | | | | | | | | | | | | The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHzPaul Walmsley2009-05-121-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | ARM: OMAP2/3: Change omapfb to use clkdev for dispc and rfbi, v2Tony Lindgren2009-05-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | This makes the framebuffer work on omap3. Also fix the clk_get usage for checkpatch.pl "ERROR: do not use assignment in if condition". Cc: Imre Deak <imre.deak@nokia.com> Cc: linux-fbdev-devel@lists.sourceforge.net Acked-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2/3: Add name for musb clocksTony Lindgren2009-05-121-1/+1
|/ | | | | | | | | | With the clkdev, musb_core.c needs to register clock with name "ick". Once all the platforms using the musb driver have been converted to use clockdev, the clock name does not need to be passed from the low-level init code. Signed-off-by: Tony Lindgren <tony@atomide.com>
* [ARM] omap: add support for bypassing DPLLsRussell King2009-02-191-19/+71
| | | | | | | | | | | | | | | | | | | | This roughly corresponds with OMAP commits: 7d06c48, 3241b19, 88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: arrange for clock recalc methods to return the rateRussell King2009-02-141-5/+7
| | | | | | | | | | | | | linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce introduces a way to "dry run" clock changes before they're committed. However, this involves putting logic to handle this into each and every recalc function, and unfortunately due to the caching, led to some bugs. Solve both of issues by making the recalc methods always return the clock rate for the clock, which the caller decides what to do with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2/3 clock: don't tinker with hardirqs when they are supposed to be ↵Paul Walmsley2009-02-081-2/+0
| | | | | | | | | | | | | | | | disabled Clock rate change code executes inside a spinlock with hardirqs disabled. The only code that should be messing around with the hardirq state should be the plat-omap/clock.c code. In the omap2_reprogram_dpllcore() case, this probably just wastes cycles, but in the omap3_core_dpll_m2_set_rate() case, this is a nasty bug. linux-omap source commit is b9b6208dadb5e0d8b290900a3ffa911673ca97ed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: create a proper tree of clocksRussell King2009-02-081-0/+3
| | | | | | | | | | | Traditionally, we've tracked the parent/child relationships between clk structures by setting the child's parent member to point at the upstream clock. As a result, when decending the tree, we have had to scan all clocks to find the children. Avoid this wasteful scanning by keeping a list of the clock's children. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: clks: call recalc after any rate changeRussell King2009-02-081-4/+0
| | | | | | | | | | | | This implements the remainder of: OMAP clock: move rate recalc, propagation code up to plat-omap/clock.c from Paul Walmsley which is not covered by the previous: [ARM] omap: move clock propagation into core omap clock code [ARM] omap: remove unnecessary calls to propagate_rate() [ARM] omap: move propagate_rate() calls into generic omap clock code commits. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2/3 clock: use standard set_rate fn in omap2_clk_arch_init()Paul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | | Use the standard clk_set_rate() function in omap2_clk_arch_init() rather than omap2_select_table_rate() -- this will ensure that clock rates are recalculated and propagated correctly after those operations are consolidated into clk_set_rate(). linux-omap source commit is 03c03330017eeb445b01957608ff5db49a7151b6. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()Paul Walmsley2009-02-081-0/+65
| | | | | | | | | | | | | | | | | | | Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code, which calls into the SRAM function omap3_sram_configure_core_dpll() to change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes on clocks upstream from the SDRC can glitch SDRAM accesses.) Use this function for the set_rate function pointer in the dpll3_m2_ck struct clk. With this function in place, PM/OPP code should be able to alter SDRAM speed via code similar to: clk_set_rate(&dpll3_m2_ck, target_rate). linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.hPaul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | Move the contents of the arch/arm/mach-omap2/memory.h file to the existing mach/sdrc.h file, and remove memory.h. Modify files which include memory.h to include asm/arch/sdrc.h instead. linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: disable DPLL autoidle while waiting for DPLL to lockPaul Walmsley2009-02-081-10/+5
| | | | | | | | | | | | | | | | | | | | | During _omap3_noncore_dpll_lock(), if a DPLL has no active downstream clocks and DPLL autoidle is enabled, the DPLL may never lock, since it will enter autoidle immediately. To resolve this, disable DPLL autoidle while locking the DPLL, and unconditionally wait for the DPLL to lock. This fixes some bugs where the kernel would hang when returning from retention or return the wrong rate for the DPLL. This patch is a collaboration with Peter de Schrijver <peter.de-schrijver@nokia.com> and Kevin Hilman <khilman@deeprootsystems.com>. linux-omap source commit is 3b7de4be879f1f4f55ae59882a5cbd80f6dcf0f0. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Peter de Schrijver <peter.de-schrijver@nokia.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_maskPaul Walmsley2009-02-081-4/+2
| | | | | | | | | | | | | | Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since OMAP2 uses two bits for DPLL IDLEST rather than one. While here, add the missing idlest_* fields for DPLL3. linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784 and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: fix DPLL jitter correction and rate programmingPaul Walmsley2009-02-081-5/+8
| | | | | | | | | | | | | | | | | Fix DPLL jitter correction programming. Previously, omap3_noncore_dpll_program() stored the FREQSEL jitter correction parameter to the wrong register. This caused jitter correction to be set incorrectly and also caused the DPLL divider to be programmed incorrectly. Also, fix DPLL divider programming. An off-by-one error existed in omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher divider than intended. linux-omap source commit is 5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP: Add CSI2 clock struct for handling it with clock APISergio Aguirre2009-02-081-0/+1
| | | | | | | | | | | Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3: move USBHOST SAR handling from clock framework to powerdomain layerPaul Walmsley2009-02-081-1/+0
| | | | | | | | | | | | | | | | | | Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that the clock was tweaking doesn't actually enable or disable a clock; it controls whether the hardware will save and restore USBHOST state when the powerdomain changes state. (That happens to coincidentally enable a clock for the duration of the operation, hence the earlier confusion.) In place of the clock, mark the USBHOST powerdomain as supporting hardware save-and-restore functionality. linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2/3: Add non-CORE DPLL rate set code and M, N programmingPaul Walmsley2009-02-081-1/+136
| | | | | | | | | | | | | | | | Add non-CORE DPLL rate set code and M,N programming for OMAP3. Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework. You may see some warnings on rate sets from the freqsel code. The table that TI presented in the 3430 TRM Rev F does not cover Fint < 750000, which definitely occurs in practice. However, the lack of this freqsel case does not appear to impair the DPLL rate change. linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: hsmmc: new short connection id namesRussell King2009-02-081-6/+6
| | | | | | ... rather than the clock names themselves. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: convert omap RNG clocks to match by devid and conidRussell King2009-02-081-1/+1
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: w1: convert omap HDQ clocks to match by devid and conidRussell King2009-02-081-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: i2c: use short connection idsRussell King2009-02-081-6/+6
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: mcbsp: convert to use fck/ick clocks directlyRussell King2009-02-081-10/+10
| | | | | | | | | | | | | Rather than introducing a special 'mcbsp_clk' with code behind it in mach-omap*/mcbsp.c to handle the SoC specifics, arrange for the mcbsp driver to be like any other driver. mcbsp requests its fck and ick clocks directly, and the SoC specific code deals with selecting the correct clock. There is one oddity to deal with - OMAP1 fiddles with the DSP clocks and DSP reset, so we move this to the two callback functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: mcspi: new short connection id namesRussell King2009-02-081-8/+8
| | | | | | ... rather than the clock names themselves. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: watchdog: convert clocks to match by devid and conidRussell King2009-02-081-2/+2
| | | | | | | This eliminates the need for separate OMAP24xx and OMAP34xx clock requesting code sections. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: convert OMAP3 to use clkdevRussell King2009-02-081-24/+244
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: move propagate_rate() calls into generic omap clock codeRussell King2009-02-081-5/+0
| | | | | | | | | propagate_rate() is recursive, so it makes sense to minimise the amount of stack which is used for each recursion. So, rather than recursing back into it from the ->recalc functions if RATE_PROPAGATES is set, do that test at the higher level. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: introduce clock operations structureRussell King2009-02-021-1/+9
| | | | | | | Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Use omap_rev() instead of system_revLauri Leukkunen2008-12-101-1/+1
| | | | | | | | | | | system_rev is meant for board revision, this patch changes all relevant instances to use the new omap_rev() function liberating system_rev to be used with ATAG_REVISION as it has been designed. Signed-off-by: Lauri Leukkunen <lauri.leukkunen@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Fix cpu detectionTony Lindgren2008-12-101-1/+1
| | | | | | | | | | | At some point omap2 changed the bits for GET_OMAP_CLASS, which broke 15xx detection on 730 as noticed by Russell King. This patch fixes omap2 cpu detection to respect the original GET_OMAP_CLASS, and simplifies the detection for 34xx. Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-all' into develRussell King2008-10-141-11/+20
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
| * ARM: OMAP2: Clockdomain: Integrate OMAP3 clocks with clockdomain codePaul Walmsley2008-08-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch integrates the OMAP3 clock tree with the clockdomain code. This patch: - marks OMAP34xx clocks with their corresponding clockdomain. - adds code to convert the clockdomain name to a clockdomain pointer in the struct clk during clk_register(). - modifies OMAP2 clock usecounting to call into the clockdomain code when clocks are enabled or disabled. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain codePaul Walmsley2008-08-191-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates an interface to the powerdomain registers in the PRM/CM modules on OMAP2/3. This interface is intended to be used by PM code, e.g., pm.c; not by device drivers directly. Each powerdomain will be defined in later patches as static structures. Also defined are dependencies between powerdomains, used for adding and removing PM_WKDEP and CM_SLEEPDEP bits. The powerdomain structures are linked into a list at boot by pwrdm_register(), similar to the OMAP clock code. The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which when enabled will emit verbose debug messages via pr_debug(). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | [ARM] Convert asm/bitops.h to linux/bitops.hRussell King2008-09-061-1/+1
|/ | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-2/+2
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functionsPaul Walmsley2008-07-031-4/+295
| | | | | | | | | | | | | | | | This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-141-2/+2
| | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Add 34xx clock codePaul Walmsley2008-04-141-0/+235
This patch add 34xx clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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