summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock34xx.c
Commit message (Collapse)AuthorAgeFilesLines
...
* [ARM] OMAP2/3 clock: use standard set_rate fn in omap2_clk_arch_init()Paul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | | Use the standard clk_set_rate() function in omap2_clk_arch_init() rather than omap2_select_table_rate() -- this will ensure that clock rates are recalculated and propagated correctly after those operations are consolidated into clk_set_rate(). linux-omap source commit is 03c03330017eeb445b01957608ff5db49a7151b6. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()Paul Walmsley2009-02-081-0/+65
| | | | | | | | | | | | | | | | | | | Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code, which calls into the SRAM function omap3_sram_configure_core_dpll() to change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes on clocks upstream from the SDRC can glitch SDRAM accesses.) Use this function for the set_rate function pointer in the dpll3_m2_ck struct clk. With this function in place, PM/OPP code should be able to alter SDRAM speed via code similar to: clk_set_rate(&dpll3_m2_ck, target_rate). linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.hPaul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | Move the contents of the arch/arm/mach-omap2/memory.h file to the existing mach/sdrc.h file, and remove memory.h. Modify files which include memory.h to include asm/arch/sdrc.h instead. linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: disable DPLL autoidle while waiting for DPLL to lockPaul Walmsley2009-02-081-10/+5
| | | | | | | | | | | | | | | | | | | | | During _omap3_noncore_dpll_lock(), if a DPLL has no active downstream clocks and DPLL autoidle is enabled, the DPLL may never lock, since it will enter autoidle immediately. To resolve this, disable DPLL autoidle while locking the DPLL, and unconditionally wait for the DPLL to lock. This fixes some bugs where the kernel would hang when returning from retention or return the wrong rate for the DPLL. This patch is a collaboration with Peter de Schrijver <peter.de-schrijver@nokia.com> and Kevin Hilman <khilman@deeprootsystems.com>. linux-omap source commit is 3b7de4be879f1f4f55ae59882a5cbd80f6dcf0f0. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Peter de Schrijver <peter.de-schrijver@nokia.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_maskPaul Walmsley2009-02-081-4/+2
| | | | | | | | | | | | | | Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since OMAP2 uses two bits for DPLL IDLEST rather than one. While here, add the missing idlest_* fields for DPLL3. linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784 and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3 clock: fix DPLL jitter correction and rate programmingPaul Walmsley2009-02-081-5/+8
| | | | | | | | | | | | | | | | | Fix DPLL jitter correction programming. Previously, omap3_noncore_dpll_program() stored the FREQSEL jitter correction parameter to the wrong register. This caused jitter correction to be set incorrectly and also caused the DPLL divider to be programmed incorrectly. Also, fix DPLL divider programming. An off-by-one error existed in omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher divider than intended. linux-omap source commit is 5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP: Add CSI2 clock struct for handling it with clock APISergio Aguirre2009-02-081-0/+1
| | | | | | | | | | | Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP3: move USBHOST SAR handling from clock framework to powerdomain layerPaul Walmsley2009-02-081-1/+0
| | | | | | | | | | | | | | | | | | Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that the clock was tweaking doesn't actually enable or disable a clock; it controls whether the hardware will save and restore USBHOST state when the powerdomain changes state. (That happens to coincidentally enable a clock for the duration of the operation, hence the earlier confusion.) In place of the clock, mark the USBHOST powerdomain as supporting hardware save-and-restore functionality. linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] OMAP2/3: Add non-CORE DPLL rate set code and M, N programmingPaul Walmsley2009-02-081-1/+136
| | | | | | | | | | | | | | | | Add non-CORE DPLL rate set code and M,N programming for OMAP3. Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework. You may see some warnings on rate sets from the freqsel code. The table that TI presented in the 3430 TRM Rev F does not cover Fint < 750000, which definitely occurs in practice. However, the lack of this freqsel case does not appear to impair the DPLL rate change. linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: hsmmc: new short connection id namesRussell King2009-02-081-6/+6
| | | | | | ... rather than the clock names themselves. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: convert omap RNG clocks to match by devid and conidRussell King2009-02-081-1/+1
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: w1: convert omap HDQ clocks to match by devid and conidRussell King2009-02-081-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: i2c: use short connection idsRussell King2009-02-081-6/+6
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: mcbsp: convert to use fck/ick clocks directlyRussell King2009-02-081-10/+10
| | | | | | | | | | | | | Rather than introducing a special 'mcbsp_clk' with code behind it in mach-omap*/mcbsp.c to handle the SoC specifics, arrange for the mcbsp driver to be like any other driver. mcbsp requests its fck and ick clocks directly, and the SoC specific code deals with selecting the correct clock. There is one oddity to deal with - OMAP1 fiddles with the DSP clocks and DSP reset, so we move this to the two callback functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: mcspi: new short connection id namesRussell King2009-02-081-8/+8
| | | | | | ... rather than the clock names themselves. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: watchdog: convert clocks to match by devid and conidRussell King2009-02-081-2/+2
| | | | | | | This eliminates the need for separate OMAP24xx and OMAP34xx clock requesting code sections. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: convert OMAP3 to use clkdevRussell King2009-02-081-24/+244
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: move propagate_rate() calls into generic omap clock codeRussell King2009-02-081-5/+0
| | | | | | | | | propagate_rate() is recursive, so it makes sense to minimise the amount of stack which is used for each recursion. So, rather than recursing back into it from the ->recalc functions if RATE_PROPAGATES is set, do that test at the higher level. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] omap: introduce clock operations structureRussell King2009-02-021-1/+9
| | | | | | | Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Use omap_rev() instead of system_revLauri Leukkunen2008-12-101-1/+1
| | | | | | | | | | | system_rev is meant for board revision, this patch changes all relevant instances to use the new omap_rev() function liberating system_rev to be used with ATAG_REVISION as it has been designed. Signed-off-by: Lauri Leukkunen <lauri.leukkunen@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Fix cpu detectionTony Lindgren2008-12-101-1/+1
| | | | | | | | | | | At some point omap2 changed the bits for GET_OMAP_CLASS, which broke 15xx detection on 730 as noticed by Russell King. This patch fixes omap2 cpu detection to respect the original GET_OMAP_CLASS, and simplifies the detection for 34xx. Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-all' into develRussell King2008-10-141-11/+20
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
| * ARM: OMAP2: Clockdomain: Integrate OMAP3 clocks with clockdomain codePaul Walmsley2008-08-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch integrates the OMAP3 clock tree with the clockdomain code. This patch: - marks OMAP34xx clocks with their corresponding clockdomain. - adds code to convert the clockdomain name to a clockdomain pointer in the struct clk during clk_register(). - modifies OMAP2 clock usecounting to call into the clockdomain code when clocks are enabled or disabled. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain codePaul Walmsley2008-08-191-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates an interface to the powerdomain registers in the PRM/CM modules on OMAP2/3. This interface is intended to be used by PM code, e.g., pm.c; not by device drivers directly. Each powerdomain will be defined in later patches as static structures. Also defined are dependencies between powerdomains, used for adding and removing PM_WKDEP and CM_SLEEPDEP bits. The powerdomain structures are linked into a list at boot by pwrdm_register(), similar to the OMAP clock code. The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which when enabled will emit verbose debug messages via pr_debug(). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | [ARM] Convert asm/bitops.h to linux/bitops.hRussell King2008-09-061-1/+1
|/ | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-2/+2
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functionsPaul Walmsley2008-07-031-4/+295
| | | | | | | | | | | | | | | | This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-141-2/+2
| | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Add 34xx clock codePaul Walmsley2008-04-141-0/+235
This patch add 34xx clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
OpenPOWER on IntegriCloud