summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-msm/board-msm8x60.c
Commit message (Collapse)AuthorAgeFilesLines
* irq_domain: Remove irq_domain_add_simple()Grant Likely2012-02-161-6/+2
| | | | | | | | | | | | | | | | | | | | | | | irq_domain_add_simple() was a stop-gap measure until complete irq_domain support was complete. This patch removes the irq_domain_add_simple() interface. This patch also drops the explicit irq_domain initialization performed by the mach-versatile code because the versatile interrupt controller already has irq_domain support built into it. This was a bug that was hanging around quietly for a while, but with the full irq_domain which actually verifies that irq_domain ranges are available it would cause the registration to fail and the system wouldn't boot. v4: Fixed number of irqs in mx5 gpio code v2: Updated to pass in host_data pointer on irq_domain allocation. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Milton Miller <miltonm@bga.com> Cc: Russell King <linux@arm.linux.org.uk> Tested-by: Olof Johansson <olof@lixom.net>
* ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLERMarc Zyngier2011-11-151-0/+4
| | | | | | | | | Convert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler. Tested-by: David Brown <davidb@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* Merge branch 'msm-fix' of git://codeaurora.org/quic/kernel/davidb/linux-msm ↵Olof Johansson2011-11-091-2/+2
|\ | | | | | | into fixes
| * msm: boards: Fix fallout from removal of machine_desc in fixupStephen Boyd2011-11-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After 0744a3ee (ARM: platform fixups: remove mdesc argument to fixup function, 2010-12-20) the fixup functions introduced in 9e775ad (ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMs, 2011-08-12) cause warnings like: arch/arm/mach-msm/board-msm8x60.c:85: warning: initialization from incompatible pointer type Fix them by removing the machine_desc argument from the fixup functions. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | Merge branch 'dt/gic' into next/dtArnd Bergmann2011-10-311-11/+25
|\ \ | |/ | | | | | | | | | | Conflicts: arch/arm/include/asm/localtimer.h arch/arm/mach-msm/board-msm8x60.c arch/arm/mach-omap2/board-generic.c
| * Merge branch 'ppi-irq-core-for-rmk' of ↵Russell King2011-10-231-11/+0
| |\ | | | | | | | | | git://github.com/mzyngier/arm-platforms into devel-stable
| | * ARM: gic: consolidate PPI handlingMarc Zyngier2011-10-231-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPI handling is a bit of an odd beast. It uses its own low level handling code and is hardwired to the local timers (hence lacking a registration interface). Instead, switch the low handling to the normal SPI handling code. PPIs are handled by the handle_percpu_devid_irq flow. This also allows the removal of some duplicated code. Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMsStephen Boyd2011-08-131-0/+25
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSMs post 8x50 have 2Mb at the beginning of RAM reserved for shared memory. Since the kernel hasn't typically been told this RAM exists, PHYS_OFFSET has been set to 0xN0200000 and the memory atags passed to the kernel have matched. This doesn't play nicely with things such as AUTO_ZRELADDR, which doesn't work at all, and dynamic phys to virt, which requires an MSM specific workaround. Work around these issues by telling the kernel RAM starts at 0xN0000000 (it actually does) and fixup the atags from the bootloader (if necessary) to say the same. In addition, make sure to set TEXT_OFFSET at least 2Mb beyond the start of RAM so that the kernel doesn't end up being decompressed into shared memory. After doing this, AUTO_ZRELADDR should work on MSM with no problems and ARM_PATCH_PHYS_VIRT_16BIT should no longer be necessary. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: msm: Add devicetree support for msm8660-surfDavid Brown2011-08-291-7/+51
|/ | | | | | | | Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
* arm: Cleanup the irq namespaceThomas Gleixner2011-03-291-1/+1
| | | | | | Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* msm: clock: Remove unused code and definitionsStephen Boyd2011-01-281-4/+0
| | | | | | | | This code is dead or otherwise useless so just remove it. Reviewed-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King2010-12-141-4/+2
| | | | | | | | | | Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: GIC: provide a single initialization function for boot CPURussell King2010-12-141-2/+1
| | | | | | | | | Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* msm: add MSM8x60 FFA supportGregory Bean2010-10-081-0/+7
| | | | | | | | The MSM8X60 FFA contains different components than the MSM8X60 SURF, and therefore requires a different ARCH type and machine ID. Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: MSM8X60 simulator board supportSteve Muckle2010-10-081-1/+9
| | | | | | | Board configuration for MSM8X60 simulation. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: add msm8x60_surf machineSteve Muckle2010-10-081-0/+7
| | | | | Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: 8x60: setup correct handlers for private interruptsAbhijeet Dharmapurikar2010-10-081-1/+1
| | | | | | | | Private Peripheral interrupts could be edge triggered or level triggered depending on the platform. Initialize handlers for these in board file. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: 8x60: gic initialization fixup for RUMISteve Muckle2010-10-081-0/+20
| | | | | | | | | | On RUMI platform STIs are not enabled by default, contrary to the GIC spec. The bits for STIs in the enable/enable clear registers are also RW instead of RO. STIs need to be enabled at initialization time. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: MSM8X60 RUMI3 board supportSteve Muckle2010-10-081-0/+58
Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
OpenPOWER on IntegriCloud