| Commit message (Collapse) | Author | Age | Files | Lines |
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Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
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This also removes mach/clock.h along the way
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This gate consists of two bits:
0b00: clk disabled
0b01: clk enabled in run mode and disabled in sleep mode
0b11: clk enabled
Currently only disabled and enabled are supported. As it's unlikely
that we find something like this in another SoC create a i.MX specific
clk helper for this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This PLL is found on i.MX6 SoCs
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This PLL is found on i.MX51 and i.MX53
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The pllv1 is found on i.MX1, i.M25, i.MX27, i.MX31 and i.MX35.
Currently only reading the rate is supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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- Add necessary #ifdefs for CONFIG_COMMON_CLOCK
- Add a global spinlock to protect the CCM registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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