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* ARM: imx: clk-vf610: get input clocks from assigned clocksStefan Agner2014-11-231-5/+16
| | | | | | | | | | | | | | | | | | | | With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk-vf610: define PLL's clock treeStefan Agner2014-11-041-42/+92
| | | | | | | | | | | | | | | | | | | So far, the required PLL's (PLL1/PLL2/PLL5) have been initialized by boot loader and the kernel code defined fixed rates according to those default configurations. Beginning with the USB PLL7 the code started to initialize the PLL's itself (using imx_clk_pllv3). However, since commit dc4805c2e78ba5a22ea1632f3e3e4ee601a1743b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver) imx_clk_pllv3 no longer takes care of the ENABLE and BYPASS bits, hence the USB PLL were not configured correctly anymore. This patch not only fixes those USB PLL's, but also makes use of the imx_clk_pllv3 for all PLL's and alignes the code with the PLL support of the i.MX6 series. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk-vf610: Add USBPHY clocksStefan Agner2014-09-161-2/+10
| | | | | | | | | This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: clk-vf610: introduce clks_init_onStefan Agner2014-09-161-0/+9
| | | | | | | | | | | | | | | | | | | At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: clk-vf610: fix FlexCAN clock gatingStefan Agner2014-07-181-2/+4
| | | | | | | | Extend the clock control for FlexCAN with the second gate which enable the clocks in the Clock Divider (CCM_CSCDR2) register too. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX clk: Move clock check function in common locationAlexander Shiyan2014-07-181-0/+2
| | | | | | | | This patch moves clock check function in common i.MX location and switch i.MX clk drivers to use this new function. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: clk-vf610: Suppress duplicate const sparse warningLiu Ying2014-03-051-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There should be no duplicate const specifiers for those static constant character string arrays defined for clock mux options. Also, the arrays are only taken as the 5th argument for the imx_clk_mux() function, which is in the type of 'const char **parents'. So, let's remove the 2nd const specifier right after 'char'. This patch fixes these sparse warnings: arch/arm/mach-imx/clk-vf610.c:66:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:67:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:68:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:69:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:70:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:71:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:72:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:73:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:74:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:75:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:76:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:77:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:78:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:79:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:80:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:81:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:83:25: warning: duplicate const arch/arm/mach-imx/clk-vf610.c:84:25: warning: duplicate const Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Add DMAMUX clock for Vybrid vf610 SoCJingchang Lu2013-12-091-0/+5
| | | | | Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: fix vf610 enet module clock selectionShawn Guo2013-07-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add VF610 clock supportJingchang Lu2013-06-171-0/+319
Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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