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path: root/arch/arm/mach-imx/clk-imx6q.c
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* ARM: imx: add gpt_3m clk for i.mx6qdlAnson Huang2014-09-161-0/+8
| | | | | | | | | | | | Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: fix register offset of pll7_usb_host gate clockShawn Guo2014-09-161-1/+1
| | | | | | | | | | | | There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <B38611@freescale.com> for spotting the error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add BYPASS support for PLL clocksShawn Guo2014-09-161-10/+57
| | | | | | | | | | | | The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for SSIShengjiu Wang2014-09-161-3/+9
| | | | | | | Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang2014-09-161-1/+4
| | | | | | | | ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: refine clock tree for ESAIShengjiu Wang2014-09-161-3/+4
| | | | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: correct gpu2d_axi and gpu3d_axi clock settingAnson Huang2014-08-181-2/+8
| | | | | | | | | | | | On i.MX6Q, gpu2d_axi and gpu3d_axi are either from AXI or AHB clock, but on i.MX6DL, gpu2d_axi and gpu3d_axi are from mmdc_ch0_axi_podf, and they can NOT be gated by mmdc_ch0_axi 's clock gate, the mux option register field(CCM_CBCMR) is marked as "Reserved" now on i.MX6DL RM, so correct these two clks setting. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targetsAlexander Shiyan2014-07-181-2/+0
| | | | | | | This patch uses clocksource_of_init() call for DT targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6qdl: switch to use macro for clock IDShawn Guo2014-07-181-282/+247
| | | | | | | | Instead of using enum for clock ID, let's switch imx6qdl clock driver to use macro. In this case, device tree can reuse these macros to improve readability. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX clk: Move clock check function in common locationAlexander Shiyan2014-07-181-4/+1
| | | | | | | | This patch moves clock check function in common i.MX location and switch i.MX clk drivers to use this new function. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case.Alexander Shiyan2014-07-181-2/+0
| | | | | | | | | Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6q: parent lvds_sel input from upstream clock gatesLucas Stach2014-07-181-2/+2
| | | | | | | | | | | | | | | | | | | | The i.MX6 reference manual doesn't make a clear distinction between the fixed clock divider and the enable gate for the pcie and sata reference clocks. This lead to the lvds mux inputs in the imx6q clk driver to be parented from the ref clock (which is the divider) instead of the actual gate, which in turn prevents the upstream clock to actually be enabled when lvds clk out is active. This fixes a hard machine hang regression in kernel 3.16 for boards where only pcie is active but no sata, as with this kernel version the imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out. Reported-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add the missing esai_ahb clockShawn Guo2014-05-121-2/+5
| | | | | | | | | | | The esai_ahb clock is derived from ahb and used to provide ESAI the capability of register accessing and FSYS clock source for I2S clocks dividing. The gate bits of this esai_ahb clock are shared with the esai clock -- the baud clock, so we need to call imx_clk_gate2_shared() for these two clocks. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6: clk: i.MX6 DualLite/Solo i2c4 clockIain Paton2014-05-121-1/+5
| | | | | | | | | | Compared to i.MX6 Quad/Dual the CCM_CCGR1 register in the i.MX6 Solo/DualLite replaces the ecspi5 clock with the i2c4 clock. Handle this difference using cpu_is_imx6dl(). Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: factor device tree timer initializationGilles Chanteperdrix2014-04-301-6/+2
| | | | | Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: ipu_di_sel clocks can set parent ratesPhilipp Zabel2014-04-151-8/+8
| | | | | | | | | To obtain exact pixel clocks, allow the DI clock selectors to influence the PLLs that they are derived from. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_selSascha Hauer2014-04-151-0/+9
| | | | | | | | | | Route the video PLL to the display interface clocks via the di_pre_sel and di_sel muxes by default. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q-clk: parent lvds_gate from lvds_selLucas Stach2014-04-141-2/+2
| | | | | | | | | | Allows fror proper refcounting of the parent clocks when enabling the clock output on CLK1/2 pads. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: support ptp and rmii clock from padShawn Guo2014-03-051-0/+1
| | | | | | | | | | | | On imx6qdl, the ENET RMII and PTP clock can come from either internal ANATOP/CCM or external clock source through pad GPIO_16. But in case of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared. The patch adds the support for systems that use an external clock source and distinguishes above two cases by checking if the PTP clock specified in device tree is the one coming from the internal ANATOP/CCM. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: remove unneeded clk lookupsShawn Guo2014-03-051-6/+0
| | | | | | | | | | | Since commit (a94f8ec ARM: imx6q: remove board specific CLKO setup), a number of clk lookups in imx6q clock driver is no longer needed. Let's remove them. The cpu0 lookup is also removed since we are now running imx6 cpufreq driver and looking up clocks from device tree. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: Initialize low-power mode early againPhilipp Zabel2014-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | Since commit 9e8147bb5ec5d1dda2141da70f96b98985a306cb "ARM: imx6q: move low-power code out of clock driver" the kernel fails to boot on i.MX6Q/D if preemption is enabled (CONFIG_PREEMPT=y). The kernel just hangs before the console comes up. The above commit moved the initalization of the low-power mode setting (enabling clocked WAIT states), which was introduced in commit 83ae20981ae924c37d02a42c829155fc3851260c "ARM: imx: correct low-power mode setting", from imx6q_clks_init to imx6q_pm_init. Now it is called much later, after all cores are enabled. This patch moves the low-power mode initialization back to imx6q_clks_init again (and to imx6sl_clks_init). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* ARM: imx6: Derive spdif clock from pll3_pfd3_454mNicolin Chen2013-12-311-0/+3
| | | | | | | | | | SPDIF can derive a TX clock for playback from one of its clock sources -- spdif root clock to match its supporting sample rates. So this patch set the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m can approximately meet its sample rate requirement. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk: correct arm clock usecountAnson Huang2013-12-311-1/+1
| | | | | | | | | | | ARM clock is sourcing from pll1_sw, and pll1_sw can be either from pll1_sys or step, so we should enable arm clock during clock initialization instead of pll1_sys, otherwise, arm clock's usecount would be incorrect and PLL1 will never be disabled even it is not used. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add missing sentinel to divider tableLothar Waßmann2013-11-111-2/+3
| | | | | | | | The clk_enet_ref_table[] is missing a final empty entry as end of list marker. Also make the existing markers more obvious. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6q: fix the wrong parent of can_root clockJiada Wang2013-11-111-1/+1
| | | | | | | | instead of pll3_usb_otg the parent of can_root clock should be pll3_60m. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: move low-power code out of clock driverShawn Guo2013-10-211-154/+2
| | | | | | | | | | | | | | The LPM (Low Power Mode) code that currently sits in imx6q clock driver will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl. In order to avoid adding another ioremap for CCM block, imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base for pm code. During the move, the unused CCGR macros get removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: clock and Kconfig update for PCIe supportSean Cross2013-10-211-0/+4
| | | | | | | Update imx6q clock initialization and Kconfig for PCIe support. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Add LVDS general-purpose clocks to i.MX6QSean Cross2013-10-211-1/+19
| | | | | | | | | The i.MX6 has two general-purpose LVDS clocks that can be driven from a variety of sources. This patch adds a mux and a gate for both of these clocks. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: use common soc revision helpersShawn Guo2013-10-211-2/+3
| | | | | | | | It calls imx_set_soc_revision() to set up soc revision in imx6q_init_revision(), and replaces all the occurrences of imx6q_revision() with common helper imx_get_soc_revision(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: Add pll4_audio_div to clock treeNicolin Chen2013-10-211-4/+5
| | | | | | | | There's a pll4_audio_div clock, an extra divider for pll4, missing in current clock tree, thus add it. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: remove board specific CLKO setupShawn Guo2013-08-221-0/+11
| | | | | | | | | | | The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add vdoa gate clockShawn Guo2013-08-221-1/+2
| | | | | | Add the missing vdoa gate clock for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add the missing cko output selectionShawn Guo2013-08-221-1/+3
| | | | | | | | The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and there is a multiplexer to select between cko1 and cko2. Add this missing selection as the clock cko. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add cko2 clocksShawn Guo2013-08-221-1/+14
| | | | | | | It adds the missing cko2 clocks, including multiplexer, divider and gate. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add spdif gate clockShawn Guo2013-08-221-1/+3
| | | | | | It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: change some clocks to fixup clocksLiu Ying2013-08-161-12/+12
| | | | | | | | | | All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DLPhilipp Zabel2013-08-161-1/+1
| | | | | | | i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6Q: correct emi_sel clock muxingLiu Ying2013-07-151-2/+3
| | | | | | | | | | | | | | The correct muxing for emi_sel clock should be 2b'00 - 396M PFD 2b'01 - PLL3 2b'10 - AXI clk root 2b'11 - 352M PFD This patch corrects the muxing in the clock driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2013-06-171-0/+2
| | | | | | | WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2013-06-171-6/+3
| | | | | | | | Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: call of_clk_init() to register fixed rate clocksShawn Guo2013-06-171-14/+5
| | | | | | | As the fixed rate clocks are defined in device tree, we can just call of_clk_init() to register them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: clk: add the eim_slow clockHuang Shijie2013-06-171-1/+2
| | | | | | | Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2013-06-171-1/+0
| | | | | | | | | | | The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk-imx6q: AXI clock select index is incorrectAnson Huang2013-06-031-1/+1
| | | | | | | | | | | | The AXI clock mux should be as below: 00: periph; 01: pll2_pfd2_396m; 10: periph; 11: pll3_pfd1_540m; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: fix for ldb_di_selsJiada Wang2013-05-231-1/+1
| | | | | | | | | | As pll5_video_div has been introduced to represent the clock generated from post-divider for video. Instead of pll5_video, pll5_video_div should be proper root clock for ldb_di_sel. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: fix typo in gpu3d_shader_selsShawn Guo2013-05-121-1/+1
| | | | | | | | There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m. Fix the typo in gpu3d_shader_sels. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM i.MX6: correct MLB clock configurationDirk Behme2013-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | According to the i.MX6 Dual/Quad technical reference manual (Figure 18-2. Clock Tree - Part 1) the MLB clock is directly feed by the AXI_CLK_ROOT. This is called 'axi' in our code. Note that the clock of the MLB IP block on the i.MX6 is completely independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible for feeding the MLB IP block with a clock. Instead, it's used internally by the MLB module to sync the bus clock in case the MLB 6-pin interface is enabled: MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN: 1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case. I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed for clocking the MLB module itself. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jiada Wang <Jiada_Wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocksPhilipp Zabel2013-05-121-3/+4
| | | | | | | | The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/ pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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