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* [PATCH] remove unused ibcs2/PER_SVR4 in SET_PERSONALITYMartin Schwidefsky2008-10-161-1/+1
| | | | | | | | The SET_PERSONALITY macro is always called with a second argument of 0. Remove the ibcs argument and the various tests to set the PER_SVR4 personality. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* Merge branch 'master' of ↵David Woodhouse2008-10-1327-603/+545
|\ | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 Conflicts: include/asm-x86/statfs.h
| * Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-10-1124-522/+536
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits) [ARM] 5300/1: fixup spitz reset during boot [ARM] 5295/1: make ZONE_DMA optional [ARM] 5239/1: Palm Zire 72 power management support [ARM] 5298/1: Drop desc_handle_irq() [ARM] 5297/1: [KS8695] Fix two compile-time warnings [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores. [ARM] pxa: allow multi-machine PCMCIA builds [ARM] pxa: add preliminary CPUFREQ support for PXA3xx [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c [ARM] pxa/zylonite: add support for USB OHCI [ARM] ohci-pxa27x: use ioremap() and offset for register access [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph() [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c [ARM] pxa: simplify DMA register definitions [ARM] pxa: make additional DCSR bits valid for PXA3xx [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c ... Fixed up conflicts in arch/arm/mach-versatile/core.c sound/soc/pxa/pxa2xx-ac97.c sound/soc/pxa/pxa2xx-i2s.c manually.
| | * Merge branch 'for-rmk' of git://source.mvista.com/git/linux-davinci-2.6.gitRussell King2008-10-091-1/+1
| | |\ | | | | | | | | | | | | Merge branch 'davinci' into devel
| | * \ Merge branch 'pxa-all' into develRussell King2008-10-091-2/+1
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/corgi.c arch/arm/mach-pxa/include/mach/hardware.h arch/arm/mach-pxa/spitz.c
| | | * \ Merge branches 'pxa-core' and 'pxa-machines' into pxa-allRussell King2008-10-072-8/+11
| | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c
| | | * | | [ARM] pxa: remove references to pxa_gpio_mode() in commentsRussell King2008-09-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | Merge branch 'at91' into develRussell King2008-10-091-11/+14
| | |\ \ \ \ | | | | |/ / | | | |/| |
| | * | | | Merge branch 'ptebits' into develRussell King2008-10-096-87/+105
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig
| | | * | | | [ARM] Improve non-executable supportRussell King2008-10-013-56/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for detecting non-executable stack binaries, and adjust permissions to prevent execution from data and stack areas. Also, ensure that READ_IMPLIES_EXEC is enabled for older CPUs where that is true, and for any executable-stack binary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-011-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Remove MT_NONSHARED_DEVICE aliasRussell King2008-10-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use MT_DEVICE_NONSHARED instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-013-12/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-011-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Convert Xscale and Xscale3 to use new memory typesRussell King2008-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Introduce new PTE memory type bitsRussell King2008-10-011-5/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide L_PTE_MT_xxx definitions to describe the memory types that we use in Linux/ARM. These definitions are carefully picked such that: 1. their LSBs match what is required for pre-ARMv6 CPUs. 2. they all have a unique encoding, including after modification by build_mem_type_table() (the result being that some have more than one combination.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | [ARM] Re-jig Linux PTE bits to allow room for 4 memory type bitsRussell King2008-10-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5295/1: make ZONE_DMA optionalNicolas Pitre2008-10-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most ARM machines don't need a special "DMA" memory zone, and when configured out, the kernel becomes a bit smaller: | text data bss dec hex filename |3826182 102384 111700 4040266 3da64a vmlinux |3823593 101616 111700 4036909 3d992d vmlinux.nodmazone This is because the system now has only one zone total which effect is to optimize away many conditionals in page allocation paths. So let's configure this zone only on machines that need split zones. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] mm: enable sparsemem on clps7500 and RiscPCRussell King2008-10-011-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] mm: provide helpers for accessing membanksRussell King2008-10-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide helpers for getting physical addresses or pfns from the meminfo array, and use them. Move for_each_nodebank() to asm/setup.h alongside the meminfo structure definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.cRussell King2008-09-301-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no point scattering this around the tree, the parsing of the parameter might as well live beside the code which uses it. That also means we can make vmalloc_reserve a static variable. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5271/1: get rid of pages_to_mb()Nicolas Pitre2008-09-301-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no use of this in the whole tree. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: fix some comments in dma-mapping.hRussell King2008-09-301-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to prevent people being mislead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: don't touch cache on dma_*_for_cpu()Russell King2008-09-301-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the dma_unmap_* calls, we don't touch the cache when a DMA buffer transitions from device to CPU ownership. Presently, no problems have been identified with speculative cache prefetching which in itself is a new feature in later architectures. We may have to revisit the DMA API later for these architectures anyway. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: add validation of DMA paramsRussell King2008-09-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validate the direction argument like x86 does. In addition, validate the dma_unmap_* parameters against those passed to dma_map_* when using the DMA bounce code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: coding style cleanupsRussell King2008-09-291-56/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: fix dmabounce dma_sync_xxx() implementationsRussell King2008-09-291-15/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dmabounce dma_sync_xxx() implementation have been broken for quite some time; they all copy data between the DMA buffer and the CPU visible buffer no irrespective of the change of ownership. (IOW, a DMA_FROM_DEVICE mapping copies data from the DMA buffer to the CPU buffer during a call to dma_sync_single_for_device().) Fix it by getting rid of sync_single(), moving the contents into the recently created dmabounce_sync_for_xxx() functions and adjusting appropriately. This also makes it possible to properly support the DMA range sync functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: use new dmabounce_sync_for_xxx() for dma_sync_single_xxx()Russell King2008-09-291-74/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: Reduce to one dma_sync_sg_* implementationRussell King2008-09-291-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] dma: provide a better dma_map_page() implementationRussell King2008-09-251-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can translate a struct page directly to a DMA address using page_to_dma(). No need to use page_address() followed by virt_to_dma(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] Update dma_map_sg()/dma_unmap_sg() APIRussell King2008-09-251-110/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the ARM DMA scatter gather APIs for the scatterlist changes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] Introduce new bitmask based cache type macrosRussell King2008-09-251-81/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than trying to (inaccurately) decode the cache type from the registers each time we need to decide what type of cache we have, use a bitmask initialized early during boot. Since the setup is a one-off initialization, we can be a little more clever and take account of the CPU architecture as well. Note that we continue to achieve the compactness on optimised kernels by forcing tests to always-false or always-true as appropriate, thereby allowing the compiler to do build-time code elimination. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] Convert asm/io.h to linux/io.hRussell King2008-09-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] sparse: quieten arch/arm/kernel/irq.cRussell King2008-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] remove pc_pointer()Russell King2008-09-062-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pc_pointer() was a function to mask the PC for 26-bit ARMs, which we no longer support. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5230/1: Replace post-indexed LDRT/STRT in uaccess.hCatalin Marinas2008-09-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The post-index immediate value is optional if it is 0 and this patch removes it. The reason is to allow such instructions to compile to Thumb-2 where only pre-indexed LDRT/STRT instructions are allowed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5222/1: Allow configuring user:kernel split via KconfigLennert Buytenhek2008-09-011-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a config option (CONFIG_VMSPLIT_*) to allow choosing between 3:1, 2:2 and 1:3 user:kernel memory splits. Tested-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5211/2: fix a couple warnings from BUG() usageNicolas Pitre2008-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_DEBUG_BUGVERBOSE is not set, we get warnings such as: arch/arm/mm/ioremap.c: In function ‘remap_area_pte’: arch/arm/mm/ioremap.c:67: warning: control reaches end of non-void function mm/bootmem.c: In function ‘mark_bootmem’: mm/bootmem.c:321: warning: control reaches end of non-void function fs/dcache.c: In function ‘d_materialise_unique’: fs/dcache.c:1875: warning: control reaches end of non-void function fs/nfs/client.c: In function ‘nfs_sockaddr_match_ipaddr’: fs/nfs/client.c:251: warning: control reaches end of non-void function block/cfq-iosched.c: In function ‘cfq_async_queue_prio’: block/cfq-iosched.c:1501: warning: control reaches end of non-void function Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5218/1: arm: improved futex supportMikael Pettersson2008-09-011-3/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux/ARM currently doesn't support robust or PI futexes. The problem is that the kernel wants to perform certain ops (cmpxchg, set, add, or, andn, xor) atomically on user-space addresses, and ARM's futex.h doesn't support that. This patch adds that support, but only for uniprocessor machines. For UP it's enough to disable preemption to ensure mutual exclusion with other software agents (futexes don't need to care about other hardware agents, fortunately). This patch is based on one posted by Khem Raj on 2007-08-01 <http://marc.info/?l=linux-arm-kernel&m=118599407413016&w=2>. (That patch is included in the -RT kernel patches.) My changes since that version include: * corrected implementation of FUTEX_OP_ANDN (must complement oparg) * added missing memory clobber to futex_atomic_cmpxchg_inatomic() * removed spinlock because it's unnecessary for UP and insufficient for SMP, instead the code is restricted to UP and relies on the fact that pagefault_disable() also disables preemption * coding style cleanups Tested on ARMv5 XScales with the glibc-2.6 nptl test suite. Tested-by: Bruce Ashfield <bruce.ashfield@windriver.com> Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] 5206/1: remove kprobe_trap_handler() hackNicolas Pitre2008-09-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mentioned in commit 796969104cab0d454dbc792ad0d12a4f365a8564, and because of commit b03a5b7559563dafdbe52f8b5d8e453a914db941, the direct calling of kprobe_trap_handler() can be removed. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] cachetype: move definitions to separate headerRussell King2008-09-013-90/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than pollute asm/cacheflush.h with the cache type definitions, move them to asm/cachetype.h, and include this new header where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | [ARM] cputype: separate definitions, use themRussell King2008-09-012-58/+64
| | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add asm/cputype.h, moving functions and definitions from asm/system.h there. Convert all users of 'processor_id' to the more efficient read_cpuid_id() function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: Delete ARM's own cnt32_to_63.hDavid Howells2008-09-261-78/+0
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete ARM's own cnt32_to_63.h as the copy in include/linux/ should now be used instead. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | | | [ARM] Fix PCI_DMA_BUS_IS_PHYS for ARMRussell King2008-09-131-1/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI_DMA_BUS_IS_PHYS was defined to be zero, which meant we ignored the DMA mask for IDE and SCSI transfers. This is wrong - we have no DMA translation hardware. We want to obey DMA masks so that the block layer performs bouncing itself. Reported-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-09-082-8/+11
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 5241/1: provide ioremap_wc() [ARM] omap: fix virtual vs physical address space confusions [ARM] remove unused #include <version.h> [ARM] omap: fix build error in ohci-omap.c [ARM] omap: fix gpio.c build error
| | * | [ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek2008-09-062-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Revert "[ARM] use the new byteorder headers"David Woodhouse2008-09-051-11/+14
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ae82cbfc8beaa69007aa09966d3983ac938c3577. It needs the new byteorder headers to be exported to userspace, and they aren't yet -- and probably shouldn't be, at this point in the 2.6.27 release cycle (or ever, for that matter). Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: Use <asm-generic/statfs.h>David Woodhouse2008-09-041-32/+2
|/ / | | | | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* | [ARM] use the new byteorder headersHarvey Harrison2008-08-271-14/+11
|/ | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-08-166-36/+91
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (38 commits) [ARM] 5191/1: ARM: remove CVS keywords [ARM] pxafb: fix the warning of incorrect lccr when lcd_conn is specified [ARM] pxafb: add flag to specify output format on LDD pins when base is RGBT16 [ARM] pxafb: fix the incorrect configuration of GPIO77 as ACBIAS for TFT LCD [ARM] 5198/1: PalmTX: PCMCIA fixes [ARM] Fix a pile of broken watchdog drivers [ARM] update mach-types [ARM] 5196/1: fix inline asm constraints for preload [ARM] 5194/1: update .gitignore [ARM] add proc-macros.S include to proc-arm940 and proc-arm946 [ARM] 5192/1: ARM TLB: add v7wbi_{possible,always}_flags to {possible,always}_tlb_flags [ARM] 5193/1: Wire up missing syscalls [ARM] traps: don't call undef hook functions with spinlock held [ARM] 5183/2: Provide Poodle LoCoMo GPIO names [ARM] dma-mapping: provide sync_range APIs [ARM] dma-mapping: improve type-safeness of DMA translations [ARM] Kirkwood: instantiate the orion_spi driver in the platform code [ARM] prevent crashing when too much RAM installed [ARM] Kirkwood: Instantiate mv_xor driver [ARM] Orion: Instantiate mv_xor driver for 5182 ...
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