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* Merge branch 'for-linus' of ↵Linus Torvalds2011-10-251-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (59 commits) MAINTAINERS: linux-m32r is moderated for non-subscribers linux@lists.openrisc.net is moderated for non-subscribers Drop default from "DM365 codec select" choice parisc: Kconfig: cleanup Kernel page size default Kconfig: remove redundant CONFIG_ prefix on two symbols cris: remove arch/cris/arch-v32/lib/nand_init.S microblaze: add missing CONFIG_ prefixes h8300: drop puzzling Kconfig dependencies MAINTAINERS: microblaze-uclinux@itee.uq.edu.au is moderated for non-subscribers tty: drop superfluous dependency in Kconfig ARM: mxc: fix Kconfig typo 'i.MX51' Fix file references in Kconfig files aic7xxx: fix Kconfig references to READMEs Fix file references in drivers/ide/ thinkpad_acpi: Fix printk typo 'bluestooth' bcmring: drop commented out line in Kconfig btmrvl_sdio: fix typo 'btmrvl_sdio_sd6888' doc: raw1394: Trivial typo fix CIFS: Don't free volume_info->UNC until we are entirely done with it. treewide: Correct spelling of successfully in comments ...
| * doc: fix broken referencesPaul Bolle2011-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | There are numerous broken references to Documentation files (in other Documentation files, in comments, etc.). These broken references are caused by typo's in the references, and by renames or removals of the Documentation files. Some broken references are simply odd. Fix these broken references, sometimes by dropping the irrelevant text they were part of. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | Merge branch 'misc' into for-linusRussell King2011-10-251-5/+6
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/mach-integrator/integrator_ap.c
| * | ARM: 7129/1: Add __arm_ioremap_exec for mapping external memory as MT_MEMORYTony Lindgren2011-10-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows mapping external memory such as SRAM for use. This is needed for some small chunks of code, such as reprogramming SDRAM memory source clocks that can't be executed in SDRAM. Other use cases include some PM related code. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 7118/1: rename temp variable in read*_relaxed()Olof Johansson2011-10-171-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | This resolves the following sparse warning from readl() and other macros, which ends up embedding readl_relaxed() using the same variable. arch/arm/mach-tegra/dma.c:169:8: warning: symbol '__v' shadows an earlier one arch/arm/mach-tegra/dma.c:169:8: originally declared here Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*-. \ Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0', ↵Russell King2011-10-251-0/+27
|\ \ \ | |_|/ |/| | | | | 'p2v', 'pgt' (early part) and 'smp' into for-linus
| | * ARM: io: add a default IO_SPACE_LIMIT definitionRussell King2011-08-171-0/+21
| |/ |/| | | | | | | | | | | Add a default IO_SPACE_LIMIT definition. Explain the chosen value and suggest why platforms would want to make it larger. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: add io{read,write}{16,32}be functionsArnd Bergmann2011-10-011-0/+6
|/ | | | | | | These functions are used in some PCI drivers with big-endian MMIO space, and they are trivial to add here. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+Russell King2011-01-311-16/+17
| | | | | | | | | | | Ensure that the ISA/PCI IO space accessors are properly ordered on ARMv6+ architectures. These should always be ordered with respect to all other accesses. This also fixes __iormb() and __iowmb() not being visible to ioread/ iowrite if a platform defines its own MMIO accessors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: io: simplify ioremap* and iounmap definitionsRussell King2010-12-081-7/+4
| | | | | | | | | | We don't need to repeat the same definitions of the ioremap*(), once in terms of __arch_ioremap() and again in terms of __arm_ioremap(). Instead, if the platform hasn't provided an __arch_ioremap, define this to be __arm_ioremap, and only define the ioremap*() set using __arch_ioremap. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: io: make iounmap() a simple macroRussell King2010-12-081-2/+2
| | | | | | | | | | Defining iounmap() with arguments prevents it from being used as a function pointer, causing platforms to work around this. Instead, define it to be a simple macro. Do the same for __arch_io(re|un)map too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: implement CONFIG_STRICT_DEVMEM by disabling access to RAM via /dev/memNicolas Pitre2010-10-011-0/+1
| | | | | | | | There are very few legitimate use cases, if any, for directly accessing system RAM through /dev/mem. So let's mimic what they do on x86 and forbid it when CONFIG_STRICT_DEVMEM is turned on. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: Add barriers to io{read,write}{8,16,32} accessors as wellRussell King2010-07-291-20/+18
| | | | | | | | | The ioread/iowrite accessors also need barriers as they're used in place of readl/writel et.al. in portable drivers. Create __iormb() and __iowmb() which are conditionally defined to be barriers dependent on ARM_DMA_MEM_BUFFERABLE, and always use these macros in the accessors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6273/1: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLECatalin Marinas2010-07-291-0/+11
| | | | | | | | | | | | | | | | | | | | | | | When the coherent DMA buffers are mapped as Normal Non-cacheable (ARM_DMA_MEM_BUFFERABLE enabled), buffer accesses are no longer ordered with Device memory accesses causing failures in device drivers that do not use the mandatory memory barriers before starting a DMA transfer. LKML discussions led to the conclusion that such barriers have to be added to the I/O accessors: http://thread.gmane.org/gmane.linux.kernel/683509/focus=686153 http://thread.gmane.org/gmane.linux.ide/46414 http://thread.gmane.org/gmane.linux.kernel.cross-arch/5250 This patch introduces a wmb() barrier to the write*() I/O accessors to handle the situations where Normal Non-cacheable writes are still in the processor (or L2 cache controller) write buffer before a DMA transfer command is issued. For the read*() accessors, a rmb() is introduced after the I/O to avoid speculative loads where the driver polls for a DMA transfer ready bit. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6271/1: Introduce *_relaxed() I/O accessorsCatalin Marinas2010-07-291-12/+17
| | | | | | | | | | | | This patch introduces readl*_relaxed()/write*_relaxed() as the main I/O accessors (when __mem_pci is defined). The standard read*()/write*() macros are now based on the relaxed accessors. This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add caller information to ioremapRussell King2010-02-151-2/+9
| | | | | | | | | This allows the procfs vmallocinfo file to show who created the ioremap regions. Note: __builtin_return_address(0) doesn't do what's expected if its used in an inline function, so we leave __arm_ioremap callers in such places alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add a common typesafe __io implementationRussell King2008-11-301-0/+8
| | | | | | | | As Al did for Versatile in 2ad4f86b60b649fd7428265c08d73a3bd360c81b, add a typesafe __io implementation for platforms to use. Convert platforms to use this new simple typesafe implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-011-3/+2
| | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek2008-09-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-1/+1
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-021-0/+287
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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