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* ARM: vf610: add second DSPI instanceBhuvanchandra DV2015-03-301-0/+11
| | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: vf610: use zero based naming for GPIO nodesStefan Agner2015-01-201-10/+10
| | | | | | | | | | | On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vfxxx: Add SNVS nodeSanchayan Maity2015-01-131-0/+14
| | | | | | | | | Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: add system reset controller and syscon-rebootStefan Agner2015-01-051-0/+12
| | | | | | | | | Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: enable watchdog for Cortex-A5 dt'sStefan Agner2015-01-051-1/+1
| | | | | | | | | | During restructuring of the device tree files the watchdog was changed to be disabled by default. However, since the watchdog instance is dedicated to the Cortex-A5, enable the peripheral by default in the base device tree vf500.dtsi. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: use new GPIO supportStefan Agner2014-11-231-0/+1
| | | | | | | | | | Use GPIO support by adding SD card detection configuration and GPIO pinmux for Colibri's standard GPIO pins. Attach the GPIO pins to the iomuxc node to get the GPIO pin settings applied. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: create generic base device treesStefan Agner2014-11-231-0/+436
This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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