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* ARM: dts: vf610: create generic base device treesStefan Agner2014-11-231-492/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: assign oscillator to clock moduleStefan Agner2014-11-231-14/+11
| | | | | | | | | | | | | | The clock controller module (CCM) has several clock inputs, which are connected to external crystal oscillators. To reflect this, assign these fixed clocks to the CCM node directly. This especially resolves initialization order dependencies we had with the earlier initialization code: When resolving of the fixed clocks failed in clk-vf610, the code created fixed clocks with a rate of 0. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: Add PWM second instanceBhuvanchandra DV2014-11-231-0/+13
| | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: Add ARM Global TimerStefan Agner2014-11-231-0/+8
| | | | | | | | | | | Add Global Timer support which is part of the private peripherals of the Cortex-A5 processor. This Global Timer is compatible with the Cortex-A9 implementation. It's a 64-bit timer and is clocked by the peripheral clock, which is typically 133 or 166MHz on Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: Add usbmisc for non-core registersStefan Agner2014-09-161-1/+15
| | | | | | | | | Add device tree node for usbmisc which controls the non-core USB registers. This is required to use the property to disable the over- current detection. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: Add USB PHY and controllerStefan Agner2014-09-161-3/+43
| | | | | | | | | | | | This adds USB PHY and USB controller nodes. Vybrid SoCs have two independent USB cores which each supports DR (dual role). However, real OTG is not supported since the OTG ID pin is not available. The PHYs are located within the anadig register range, hence we need to change the length of the anadig registers. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: add FlexCAN nodeStefan Agner2014-07-181-0/+23
| | | | | | | Add FlexCAN node for the two FlexCAN IP instances in Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: fix length of eshdc1 register propertyStefan Agner2014-07-181-1/+1
| | | | | Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* Merge branch 'timers-core-for-linus' of ↵Linus Torvalds2014-06-041-0/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next Pull timer core updates from Thomas Gleixner: "This time you get nothing really exciting: - A huge update to the sh* clocksource drivers - Support for two more ARM SoCs - Removal of the deprecated setup_sched_clock() API - The usual pile of fixlets all over the place" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) clocksource: Add Freescale FlexTimer Module (FTM) timer support ARM: dts: vf610: Add Freescale FlexTimer Module timer node. clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation clocksource: sh_tmu: Remove unnecessary OOM messages clocksource: sh_mtu2: Remove unnecessary OOM messages clocksource: sh_cmt: Remove unnecessary OOM messages clocksource: em_sti: Remove unnecessary OOM messages clocksource: dw_apb_timer_of: Do not trace read_sched_clock clocksource: Fix clocksource_mmio_readX_down clocksource: Fix type confusion for clocksource_mmio_readX_Y clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case clocksource: qcom: Implement read_current_timer for udelay ntp: Make is_error_status() use its argument ntp: Convert simple_strtol to kstrtol timer_stats/doc: Fix /proc/timer_stats documentation sched_clock: Remove deprecated setup_sched_clock() API ARM: sun6i: a31: Add support for the High Speed Timers clocksource: sun5i: Add support for reset controller clocksource: efm32: use $vendor,$device scheme for compatible string KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform ...
| * ARM: dts: vf610: Add Freescale FlexTimer Module timer node.Xiubo Li2014-05-231-0/+13
| | | | | | | | | | | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Jingchang Lu <b35083@freescale.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | ARM: dts: vf610: Add Freescale FTM PWM node.Xiubo Li2014-05-161-0/+13
| | | | | | | | | | | | | | | | | | | | This adds devicetree node for VF610, and there are 8 channels supported. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* | ARM: dts: vf610-twr: Add support for sdhc1Cosmin Stoica2014-04-301-0/+11
|/ | | | | | | | | | | | | | | | The kernel was not able to boot from SD card because sdhc support was not present into the dts. A new entry for sdhc1 was added for vf610-twr board based on the compatible entry present on imx53. After applying these changes, the kernel is able to boot successfully from SD card. Signed-off-by: Cosmin Stoica <cosminstefan.stoica@freescale.com> Signed-off-by: Chircu Bogdan <Bogdan.Chircu@freescale.com> Signed-off-by: Eddy Petrisor <eddy.petrisor@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: imx: add required #clock-cells for fixed-clockShawn Guo2014-04-141-0/+2
| | | | | | | Per bindings of fixed-clock, #clock-cells is a required property. Let's add it for those fixed rate clocks. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vybrid: drop address and size cells from GIC nodeLucas Stach2014-04-141-2/+0
| | | | | | | | | | | | | This is likely a copy-and-paste error from the ARM GIC documentation, that has already been fixed. address-cells should have been set to 0, as with the size cells. As having those properties set to 0 is the same thing as not specifying them, drop them completely. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: vf610: i2c: Add eDMA supportYuan Yao2014-02-271-0/+3
| | | | | | | Add i2c dts node properties for eDMA support, them depend on the eDMA driver. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610-twr: Add ADC supportFugang Duan2014-02-241-0/+18
| | | | | | | | | | | | | | | | vf610 has two ADC controllers, and vf610-twr board ADC0_SE5 pin connect to sliding rheostat for ADC test, other ADC pins connect to connectors for future use. Add support for ADC0_SE5. CC: Jonathan Cameron <jic23@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: Otavio Salvador <otavio@ossystems.com.br> CC: Peter Meerwald <pmeerw@pmeerw.net> CC: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: Add edma mux Tx and Rx support for SAI node.Xiubo Li2014-02-201-0/+3
| | | | | | | This patch adds the SAI's edma mux Tx and Rx support. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: lpuart: Add eDMA supportYuan Yao2014-02-181-0/+12
| | | | | | | | Add lpuart dts node properties for eDMA support, them depend on the eDMA driver. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: Add eDMA nodeJingchang Lu2014-02-181-0/+30
| | | | | | Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: use the interrupt macrosHuang Shijie2014-02-091-18/+19
| | | | | | | | | | | | This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace the hardcode. [shawn.guo: While at it, we also fix the typo in uart0 interrupts property, where the 0x00 should 0x04. Hense, it should also be IRQ_TYPE_LEVEL_HIGH just like other UART instances.] Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: make pinctrl nodes board specificShawn Guo2014-02-091-170/+0
| | | | | | | | | | | | | | | | | | | | Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Fugang Duan <B38611@freescale.com>
* ARM: dts: vf610: Add DSPI nodesChao Fu2013-09-261-0/+12
| | | | | | | Add Freescale DSPI node into vf610 dts. Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: fix vf610 enet module clock selectionShawn Guo2013-07-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: mxc: fix gpio-ranges for VF610Stephen Warren2013-06-171-6/+6
| | | | | | | | | | | The gpio-ranges properties in vf610.dtsi were written according to an older version of the GPIO bindings. Unfortunately, these were changed incompatibly in commit 86853c8 "gpio: add gpio offset in gpio range cells property". This patch adds the missing required extra cell in each gpio-ranges property. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: add SoC level device tree source for VF610Jingchang Lu2013-06-171-0/+464
Add SoC level device tree source for Freescale Vybrid VF610. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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