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* Merge tag 'tegra-for-3.16-dt' of ↵Olof Johansson2014-05-211-0/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Merge "ARM: tegra: device tree changes for 3.16" from Stephen Warren: The bulk of Tegra changes for 3.16 are to device trees. Highlights are: - New board support for: - Jetson TK1. - SHIELD. - Tegra Note 7. - Colibri T30 module. - HDMI support on Venice2. - SD card write-protect GPIOs added to some boards. - Numerous regulator cleanups. * tag 'tegra-for-3.16-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: initial add of Colibri T30 ARM: tegra: add device tree for SHIELD ARM: tegra: add SD wp-gpios to Venice2 DT ARM: tegra: add Tegra Note 7 device tree ARM: tegra: add SD wp-gpios to Dalmore DT ARM: tegra: add SD wp-gpios to Jetson TK1 DT ARM: tegra: use correct audio CODEC on Jetson TK1 ARM: tegra: dalmore - Add DSI power supply ARM: tegra: dalmore - Add +5V HDMI supply ARM: tegra: beaver - Add +5V HDMI supply ARM: tegra: harmony - Add +5V HDMI supply ARM: tegra: jetson-tk1 - Enable HDMI support ARM: tegra: venice2 - Enable HDMI ARM: tegra: Add Tegra124 HDMI support ARM: tegra: fix Venice2 SD card VQMMC supply ARM: tegra: make Venice's +3.3V_RUN regulator always on ARM: tegra: fix Jetson TK1 SD card supply ARM: tegra: define Jetson TK1 regulators ARM: tegra: add Jetson TK1 device tree Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: Add Tegra124 HDMI supportThierry Reding2014-04-281-0/+12
| | | | | | | | | | | | | | Add a device node for the HDMI controller found on Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: remove UART5/UARTE from tegra124.dtsiStephen Warren2014-04-241-13/+0
|/ | | | | | | | | | Tegra124 only has 4 UARTs. Parts of the documentation hint at a fifth UART, but this appears to be left-over from earlier SoC documentation. Remove the non-existent DT node for UART5. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: tegra: use 2 address cells for Tegra124 DTStephen Warren2014-03-051-105/+110
| | | | | | | | | | | Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra124 USB supportThierry Reding2014-02-281-0/+99
| | | | | | | | The USB controllers on Tegra124 are backwards-compatible with those found on Tegra30. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra124 eDP supportThierry Reding2014-02-281-0/+26
| | | | | | | | The SOR block on Tegra124 can be used standalone to drive LVDS panels or used in conjunction with the DPAUX block to support eDP. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra124 host1x supportThierry Reding2014-02-281-0/+41
| | | | | | | | | | The version of host1x on Tegra124 is largely compatible with that on earlier Tegra generations. Some of the registers have moved around or expanded to allow for more capability, so a separate compatible string is still required. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Use "disabled" for status propertyThierry Reding2014-02-251-4/+4
| | | | | | | | To disable a device tree node, the status property should be set to "disabled", not "disable". Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add SPI controller nodes for Tegra124Thierry Reding2013-12-161-0/+90
| | | | | | | | The SPI controllers on Tegra124 are compatible with those found on the Tegra114 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add default pinctrl nodes for Venice2Laxman Dewangan2013-12-161-0/+1
| | | | | | | | Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra124 PWM supportThierry Reding2013-12-161-0/+10
| | | | | | | | | The PWM controller on Tegra124 is the same as the one on earlier SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren, added reset properties] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add audio-related device to Tegra124 DTStephen Warren2013-12-161-0/+103
| | | | | | | | | Tegra124 contains a similar set of audio devices to previous Tegra chips. Specifically, there is an AHUB device which contains DMA FIFOs and audio routing, and which hosts various audio-related components such as I2S controllers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add I2C controllers to Tegra124 DTStephen Warren2013-12-161-0/+90
| | | | | | | Tegra124 has 6 I2C controllers. The first 5 have identical configuration to Tegra114, but the sixth obviously has different interrupt/... IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add MMC controllers to Tegra124 DTStephen Warren2013-12-161-0/+40
| | | | | | | | | | | | | | Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: add Tegra124 pinmux node to DTStephen Warren2013-12-161-0/+6
| | | | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked by: Laxman Dewangan <ldewangan@nvidia.com>
* ARM: tegra: add APB DMA controller to Tegra124 DTStephen Warren2013-12-161-0/+51
| | | | | | | | | Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: add reset properties to Tegra124 DTsStephen Warren2013-12-161-0/+11
| | | | | | | | | The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: add clock properties for devices of Tegra124Joseph Lo2013-12-161-0/+16
| | | | | | | | | This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add GPIO controller to tegra124.dtsiStephen Warren2013-10-151-0/+18
| | | | | | | | The Tegra124 GPIO controller is identical to Tegra30, so copy the DT node from tegra30.dtsi to tegra124.dtsi. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: enable Tegra RTC as default for Tegra124Joseph Lo2013-10-111-1/+0
| | | | | | | This patch makes the Tegra RTC enabled as default for Tegra124 platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add initial device tree for Tegra124Joseph Lo2013-10-081-0/+132
Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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