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* Merge tag 'tegra-for-3.15-dt' of ↵Olof Johansson2014-03-201-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Merge "ARM: tegra: device tree changes for 3.15" from Stephen Warren: This enables: - host1x and eDP support on Tegra124. - LCD panel support for a few Tegra20 devices and Venice2. - Enables power down, SPI flash, and USB on Venice2. - Documents which Dalmore revision is supported. - Adds an I2C bus mux to Cardhu. Additionally, Tegra124 is converted to use #address-cells=<2> since the HW suports more than 32-bits of address space, and various cleanups are included. * tag 'tegra-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (21 commits) ARM: dts: tegra: add PCIe interrupt mapping properties ARM: tegra: use 2 address cells for Tegra124 DT ARM: tegra: Rename as3722 node to pmic ARM: tegra: Fix whitespace around '=' ARM: tegra: Enable USB on Venice2 ARM: tegra: Add Tegra124 USB support ARM: tegra: Enable eDP for Venice2 ARM: tegra: Add Tegra124 eDP support ARM: tegra: Add Tegra124 host1x support ARM: tegra: Hook up SDMMC3 power-supply on Venice2 ARM: tegra: Overhaul Venice2 regulators ARM: tegra: Combine VBUS enable pins into one node ARM: tegra: Use "disabled" for status property ARM: tegra: add SPI flash to Venice2 DT ARM: tegra: enable PCA9546 on Cardhu ARM: tegra: enable LCD panel on Ventana ARM: tegra: enable LCD panel on Seaboard ARM: tegra: add system-power-controller property for PMIC node ARM: tegra: document which Dalmore revisions are supported ARM: tegra: Properly sort clocks property ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: Use "disabled" for status propertyThierry Reding2014-02-251-4/+4
| | | | | | | | | | | | | | | | To disable a device tree node, the status property should be set to "disabled", not "disable". Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add head numbers to display controllersThierry Reding2014-02-181-0/+4
|/ | | | | | | | | | The number of the head specifies the index of the display controller unit and is required to properly configure outputs so that they receive video data from the correct source. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: Add Tegra114 gr3d supportThierry Reding2013-12-191-0/+8
| | | | | | | | Add the gr3d device tree node. The gr3d block on Tegra114 is backwards- compatible with the one on Tegra20. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra114 gr2d supportThierry Reding2013-12-191-0/+9
| | | | | | | Add the device tree for the gr2d hardware found on Tegra114 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra114 DSI supportThierry Reding2013-12-191-0/+32
| | | | | | | Add device tree nodes for the DSI controllers found on Tegra114 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add host1x, DC and HDMI to Tegra114 device treeMikko Perttunen2013-12-191-0/+57
| | | | | | | | | Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add MIPI calibration DT entries for Tegra114Thierry Reding2013-12-191-0/+7
| | | | | | | | | | | Add a device node for the MIPI calibration block on Tegra114. There is no need to disable it by default because it only enables the clock while performing calibration and therefore shouldn't be consuming any power when unused. Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren, add unit address to new DT node name] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl definesLaxman Dewangan2013-12-161-0/+1
| | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra114 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add missing unit addresses to DTStephen Warren2013-12-161-12/+12
| | | | | | | | | | DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: remove legacy DMA entries from DTStephen Warren2013-12-111-14/+0
| | | | | | | | | Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: remove legacy clock entries from DTStephen Warren2013-12-111-15/+2
| | | | | | | | | Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-111-0/+45
| | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-111-4/+79
| | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix Tegra114 IOMMU register addressHiroshi Doyu2013-10-301-3/+3
| | | | | | | | | | | | | | | | | The IOMMU node's reg property contains completely bogus values! Somehow, this had no practical effect, despite the fact the IOMMU driver appears to be writing to those registers. I suppose that since no HW modules is actually at that address, the writes simply had no effect. Note that I'm not CCing stable here, even though the problem exists as far back as v3.9, simply because this patch doesn't fix any observed issue, and I don't want to run the risk of suddenly writing to some registers and causing a regression. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, wrote commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: add USB DT entries for Tegra114, DalmoreMikko Perttunen2013-08-131-0/+62
| | | | | | | | Device tree entries for the three EHCI controllers on Tegra114. Enables the the third controller (USB host) on Dalmore. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add audio-related nodes to Tegra114 DTStephen Warren2013-05-281-0/+71
| | | | | | Add nodes for the Tegra114 AHUB and I2S controllers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra114: convert device tree files to use CLK definesHiroshi Doyu2013-05-281-25/+26
| | | | | | | | | | | | Use the Tegra114 CAR binding header (tegra114-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use IRQ definesStephen Warren2013-05-281-72/+79
| | | | | | Use the GIC and standard IRQ binding defines in all IRQ specifiers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use GPIO definesStephen Warren2013-05-281-0/+2
| | | | | | | Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties, and some interrupts properties. Use standard GPIO flag defines too. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: use #include for all device treesStephen Warren2013-05-281-1/+1
| | | | | | | | | | | | | Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add SPI nodes to Tegra114 DTLaxman Dewangan2013-04-041-0/+72
| | | | | | | | | | | | NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add KBC nodes to Tegra114 DTLaxman Dewangan2013-04-041-0/+8
| | | | | | | | | | | NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114Laxman Dewangan2013-04-041-4/+23
| | | | | | | | | | | | | | Add APB DMA requestor and serial aliases for serial controller. There are two serial drivers i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver is selected by compatible value "nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based driver is selected by compatible value "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add I2C nodes to Tegra114 DTLaxman Dewangan2013-04-041-0/+55
| | | | | | | | | | | | | | NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the following changes which makes incompatible with previous hardware: - Single clock source to I2C controller. - Interrupt support for per packet transfer. Add DT entry for I2C controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed location of status property for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add APB DMA nodes to Tegra114 DTLaxman Dewangan2013-04-041-0/+38
| | | | | | | | | | | | | | NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add PWM nodes to Tegra114 DTAndrew Chew2013-04-041-0/+8
| | | | | | | | This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add SDHCI nodes with common propertiesPritesh Raithatha2013-04-041-0/+32
| | | | | | | | | | | This patch adds in the SDHCI nodes for the busses supported on Tegra114 boards. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> [Rhyland added clk refs to & reordered sdhci nodes and removed spaces] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: Add references to tegra_car clocksPeter De Schrijver2013-04-041-1/+7
| | | | | | | | | | Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add clock source of PMC to device treesJoseph Lo2013-04-031-0/+2
| | | | | | | Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix the PMC compatible string in DTJoseph Lo2013-03-111-1/+1
| | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: DT: tegra114: add pinmux DT entryLaxman Dewangan2013-01-291-0/+6
| | | | | | | Add DT entry for pinmux and drive configuration addresses. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: DT: tegra114: add GPIO DT entryLaxman Dewangan2013-01-291-0/+17
| | | | | | | | | | | Tegra114 has the GPIO controllers with 8 GPIO bank and each bank supports 32 pins. Add DT entry for GPIO controller. Tegra114 GPIO controller is compatible with Tegra30 GPIO controller driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add SMMU entry to Tegra114 DTHiroshi Doyu2013-01-291-0/+11
| | | | | | | Add SMMU entry. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add AHB entry to Tegra114 DTHiroshi Doyu2013-01-281-0/+5
| | | | | | | Add AHB entry. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra114: Add new SoC base, Tegra114 SoCHiroshi Doyu2013-01-281-0/+114
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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